2 files changed, 15 insertions, 0 deletions
diff --git a/test/CodeGen/CellSPU/loads.ll b/test/CodeGen/CellSPU/loads.ll
index 03d7ad1153..4771752f5f 100644
--- a/test/CodeGen/CellSPU/loads.ll
+++ b/test/CodeGen/CellSPU/loads.ll
@@ -50,3 +50,10 @@ define i32 @load_misaligned( i32* %ptr ){
   %rv = load i32* %ptr, align 2
   ret i32 %rv
 }
+
+define <4 x i32> @load_null_vec( ) {
+;CHECK: lqa
+;CHECK: bi $lr
+	%rv = load <4 x i32>* null
+	ret <4 x i32> %rv
+}
diff --git a/test/CodeGen/CellSPU/stores.ll b/test/CodeGen/CellSPU/stores.ll
index 7e0bf06b4e..6ca5b08923 100644
--- a/test/CodeGen/CellSPU/stores.ll
+++ b/test/CodeGen/CellSPU/stores.ll
@@ -171,3 +171,11 @@ define void @store_v8( <8 x float> %val, <8 x float>* %ptr )
 	store <8 x float> %val, <8 x float>* %ptr
 	ret void
 }
+
+define void @store_null_vec( <4 x i32> %val ) {
+; FIXME - this is for some reason compiled into a il+stqd, not a sta. 
+;CHECK: stqd
+;CHECK: bi $lr
+	store <4 x i32> %val, <4 x i32>* null
+	ret void
+}