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-rw-r--r--lib/Target/IA64/IA64RegisterInfo.td7
1 files changed, 6 insertions, 1 deletions
diff --git a/lib/Target/IA64/IA64RegisterInfo.td b/lib/Target/IA64/IA64RegisterInfo.td
index 148ecb7eb3..8a9032c548 100644
--- a/lib/Target/IA64/IA64RegisterInfo.td
+++ b/lib/Target/IA64/IA64RegisterInfo.td
@@ -254,7 +254,12 @@ def GR : RegisterClass<i64, 64,
{
let Methods = [{
iterator allocation_order_end(MachineFunction &MF) const {
- return end()-7; // 7 special registers
+ int numReservedRegs=7; // the 7 special registers r0,r1,r2,r12,r13 etc
+ // we also can't allocate registers for use as locals if they're
+ // already required as 'out' registers
+ numReservedRegs+=MF.getInfo<IA64FunctionInfo>()->outRegsUsed;
+
+ return end()-numReservedRegs; // hide registers appropriately
}
}];
}