diff options
Diffstat (limited to 'lib')
24 files changed, 71 insertions, 71 deletions
diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index 278e7ad078..fe5047b4ef 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -340,8 +340,8 @@ public: class SchedulingManager: public NonCopyable { public: // publicly accessible data members - const unsigned int nslots; - const MachineSchedInfo& schedInfo; + const unsigned nslots; + const TargetSchedInfo& schedInfo; SchedPriorities& schedPrio; InstrSchedule isched; diff --git a/lib/CodeGen/InstrSched/SchedGraph.cpp b/lib/CodeGen/InstrSched/SchedGraph.cpp index 4b9ff1b936..70940682f3 100644 --- a/lib/CodeGen/InstrSched/SchedGraph.cpp +++ b/lib/CodeGen/InstrSched/SchedGraph.cpp @@ -10,7 +10,7 @@ #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Function.h" diff --git a/lib/CodeGen/InstrSched/SchedPriorities.h b/lib/CodeGen/InstrSched/SchedPriorities.h index 2b9405db9a..62e41ee4f6 100644 --- a/lib/CodeGen/InstrSched/SchedPriorities.h +++ b/lib/CodeGen/InstrSched/SchedPriorities.h @@ -15,7 +15,7 @@ #include "SchedGraph.h" #include "llvm/CodeGen/InstrScheduling.h" -#include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Target/TargetSchedInfo.h" #include "Support/hash_set" #include <list> diff --git a/lib/CodeGen/InstrSelection/InstrSelection.cpp b/lib/CodeGen/InstrSelection/InstrSelection.cpp index c7bf70c806..294ecc6813 100644 --- a/lib/CodeGen/InstrSelection/InstrSelection.cpp +++ b/lib/CodeGen/InstrSelection/InstrSelection.cpp @@ -12,7 +12,7 @@ #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Function.h" #include "llvm/iPHINode.h" diff --git a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp index 86dde076dd..d7cb439f0d 100644 --- a/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp +++ b/lib/CodeGen/InstrSelection/InstrSelectionSupport.cpp @@ -13,7 +13,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/InstrForest.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Constants.h" #include "llvm/Function.h" diff --git a/lib/CodeGen/RegAlloc/LiveRangeInfo.h b/lib/CodeGen/RegAlloc/LiveRangeInfo.h index 05e9aa8510..71fda1613f 100644 --- a/lib/CodeGen/RegAlloc/LiveRangeInfo.h +++ b/lib/CodeGen/RegAlloc/LiveRangeInfo.h @@ -25,7 +25,7 @@ class LiveRange; class MachineInstr; class RegClass; -class MachineRegInfo; +class TargetRegInfo; class TargetMachine; class Value; class Function; @@ -50,7 +50,7 @@ class LiveRangeInfo { std::vector<RegClass *> & RegClassList;// vector containing register classess - const MachineRegInfo& MRI; // machine reg info + const TargetRegInfo& MRI; // machine reg info std::vector<MachineInstr*> CallRetInstrList; // a list of all call/ret instrs diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.h b/lib/CodeGen/RegAlloc/PhyRegAlloc.h index c84ca03521..ea4f562009 100644 --- a/lib/CodeGen/RegAlloc/PhyRegAlloc.h +++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.h @@ -7,9 +7,9 @@ ===== * RegisterClasses: Each RegClass accepts a - MachineRegClass which contains machine specific info about that register + TargetRegClass which contains machine specific info about that register class. The code in the RegClass is machine independent and they use - access functions in the MachineRegClass object passed into it to get + access functions in the TargetRegClass object passed into it to get machine specific info. * Machine dependent work: All parts of the register coloring algorithm @@ -24,7 +24,7 @@ #include <map> class MachineFunction; -class MachineRegInfo; +class TargetRegInfo; class FunctionLiveVarInfo; class MachineInstr; class LoopInfo; @@ -57,7 +57,7 @@ class PhyRegAlloc: public NonCopyable { FunctionLiveVarInfo *const LVI; // LV information for this method // (already computed for BBs) LiveRangeInfo LRI; // LR info (will be computed) - const MachineRegInfo &MRI; // Machine Register information + const TargetRegInfo &MRI; // Machine Register information const unsigned NumOfRegClasses; // recorded here for efficiency diff --git a/lib/CodeGen/RegAlloc/RegClass.cpp b/lib/CodeGen/RegAlloc/RegClass.cpp index 65716cf2f2..90d3987045 100644 --- a/lib/CodeGen/RegAlloc/RegClass.cpp +++ b/lib/CodeGen/RegAlloc/RegClass.cpp @@ -14,7 +14,7 @@ using std::cerr; // createInterferenceGraph() above. //---------------------------------------------------------------------------- RegClass::RegClass(const Function *M, - const MachineRegClassInfo *Mrc, + const TargetRegClassInfo *Mrc, const ReservedColorListType *RCL) : Meth(M), MRC(Mrc), RegClassID( Mrc->getRegClassID() ), IG(this), IGNodeStack(), ReservedColorList(RCL) { diff --git a/lib/CodeGen/RegAlloc/RegClass.h b/lib/CodeGen/RegAlloc/RegClass.h index 99a84c0269..7e2103c10e 100644 --- a/lib/CodeGen/RegAlloc/RegClass.h +++ b/lib/CodeGen/RegAlloc/RegClass.h @@ -9,9 +9,9 @@ #define REG_CLASS_H #include "llvm/CodeGen/InterferenceGraph.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include <stack> -class MachineRegClassInfo; +class TargetRegClassInfo; typedef std::vector<unsigned> ReservedColorListType; @@ -24,7 +24,7 @@ typedef std::vector<unsigned> ReservedColorListType; // This is the class that contains all data structures and common algos // for coloring a particular register class (e.g., int class, fp class). // This class is hardware independent. This class accepts a hardware -// dependent description of machine registers (MachineRegInfo class) to +// dependent description of machine registers (TargetRegInfo class) to // get hardware specific info and to color an individual IG node. // // This class contains the InterferenceGraph (IG). @@ -35,7 +35,7 @@ typedef std::vector<unsigned> ReservedColorListType; //----------------------------------------------------------------------------- class RegClass { const Function *const Meth; // Function we are working on - const MachineRegClassInfo *const MRC; // corresponding MRC + const TargetRegClassInfo *const MRC; // corresponding MRC const unsigned RegClassID; // my int ID InterferenceGraph IG; // Interference graph - constructed by @@ -69,7 +69,7 @@ class RegClass { public: RegClass(const Function *M, - const MachineRegClassInfo *MRC, + const TargetRegClassInfo *MRC, const ReservedColorListType *RCL = 0); inline void createInterferenceGraph() { IG.createGraph(); } diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index 278e7ad078..fe5047b4ef 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -340,8 +340,8 @@ public: class SchedulingManager: public NonCopyable { public: // publicly accessible data members - const unsigned int nslots; - const MachineSchedInfo& schedInfo; + const unsigned nslots; + const TargetSchedInfo& schedInfo; SchedPriorities& schedPrio; InstrSchedule isched; diff --git a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp index 4b9ff1b936..70940682f3 100644 --- a/lib/Target/SparcV9/InstrSched/SchedGraph.cpp +++ b/lib/Target/SparcV9/InstrSched/SchedGraph.cpp @@ -10,7 +10,7 @@ #include "llvm/CodeGen/InstrSelection.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Function.h" diff --git a/lib/Target/SparcV9/InstrSched/SchedPriorities.h b/lib/Target/SparcV9/InstrSched/SchedPriorities.h index 2b9405db9a..62e41ee4f6 100644 --- a/lib/Target/SparcV9/InstrSched/SchedPriorities.h +++ b/lib/Target/SparcV9/InstrSched/SchedPriorities.h @@ -15,7 +15,7 @@ #include "SchedGraph.h" #include "llvm/CodeGen/InstrScheduling.h" -#include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Target/TargetSchedInfo.h" #include "Support/hash_set" #include <list> diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp index c7bf70c806..294ecc6813 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelection.cpp @@ -12,7 +12,7 @@ #include "llvm/CodeGen/InstrForest.h" #include "llvm/CodeGen/MachineCodeForInstruction.h" #include "llvm/CodeGen/MachineFunction.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/TargetMachine.h" #include "llvm/Function.h" #include "llvm/iPHINode.h" diff --git a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp index 86dde076dd..d7cb439f0d 100644 --- a/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp +++ b/lib/Target/SparcV9/InstrSelection/InstrSelectionSupport.cpp @@ -13,7 +13,7 @@ #include "llvm/CodeGen/MachineFunction.h" #include "llvm/CodeGen/InstrForest.h" #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/MachineInstrInfo.h" #include "llvm/Constants.h" #include "llvm/Function.h" diff --git a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h index 05e9aa8510..71fda1613f 100644 --- a/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h +++ b/lib/Target/SparcV9/RegAlloc/LiveRangeInfo.h @@ -25,7 +25,7 @@ class LiveRange; class MachineInstr; class RegClass; -class MachineRegInfo; +class TargetRegInfo; class TargetMachine; class Value; class Function; @@ -50,7 +50,7 @@ class LiveRangeInfo { std::vector<RegClass *> & RegClassList;// vector containing register classess - const MachineRegInfo& MRI; // machine reg info + const TargetRegInfo& MRI; // machine reg info std::vector<MachineInstr*> CallRetInstrList; // a list of all call/ret instrs diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h index c84ca03521..ea4f562009 100644 --- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h +++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.h @@ -7,9 +7,9 @@ ===== * RegisterClasses: Each RegClass accepts a - MachineRegClass which contains machine specific info about that register + TargetRegClass which contains machine specific info about that register class. The code in the RegClass is machine independent and they use - access functions in the MachineRegClass object passed into it to get + access functions in the TargetRegClass object passed into it to get machine specific info. * Machine dependent work: All parts of the register coloring algorithm @@ -24,7 +24,7 @@ #include <map> class MachineFunction; -class MachineRegInfo; +class TargetRegInfo; class FunctionLiveVarInfo; class MachineInstr; class LoopInfo; @@ -57,7 +57,7 @@ class PhyRegAlloc: public NonCopyable { FunctionLiveVarInfo *const LVI; // LV information for this method // (already computed for BBs) LiveRangeInfo LRI; // LR info (will be computed) - const MachineRegInfo &MRI; // Machine Register information + const TargetRegInfo &MRI; // Machine Register information const unsigned NumOfRegClasses; // recorded here for efficiency diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.cpp b/lib/Target/SparcV9/RegAlloc/RegClass.cpp index 65716cf2f2..90d3987045 100644 --- a/lib/Target/SparcV9/RegAlloc/RegClass.cpp +++ b/lib/Target/SparcV9/RegAlloc/RegClass.cpp @@ -14,7 +14,7 @@ using std::cerr; // createInterferenceGraph() above. //---------------------------------------------------------------------------- RegClass::RegClass(const Function *M, - const MachineRegClassInfo *Mrc, + const TargetRegClassInfo *Mrc, const ReservedColorListType *RCL) : Meth(M), MRC(Mrc), RegClassID( Mrc->getRegClassID() ), IG(this), IGNodeStack(), ReservedColorList(RCL) { diff --git a/lib/Target/SparcV9/RegAlloc/RegClass.h b/lib/Target/SparcV9/RegAlloc/RegClass.h index 99a84c0269..7e2103c10e 100644 --- a/lib/Target/SparcV9/RegAlloc/RegClass.h +++ b/lib/Target/SparcV9/RegAlloc/RegClass.h @@ -9,9 +9,9 @@ #define REG_CLASS_H #include "llvm/CodeGen/InterferenceGraph.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include <stack> -class MachineRegClassInfo; +class TargetRegClassInfo; typedef std::vector<unsigned> ReservedColorListType; @@ -24,7 +24,7 @@ typedef std::vector<unsigned> ReservedColorListType; // This is the class that contains all data structures and common algos // for coloring a particular register class (e.g., int class, fp class). // This class is hardware independent. This class accepts a hardware -// dependent description of machine registers (MachineRegInfo class) to +// dependent description of machine registers (TargetRegInfo class) to // get hardware specific info and to color an individual IG node. // // This class contains the InterferenceGraph (IG). @@ -35,7 +35,7 @@ typedef std::vector<unsigned> ReservedColorListType; //----------------------------------------------------------------------------- class RegClass { const Function *const Meth; // Function we are working on - const MachineRegClassInfo *const MRC; // corresponding MRC + const TargetRegClassInfo *const MRC; // corresponding MRC const unsigned RegClassID; // my int ID InterferenceGraph IG; // Interference graph - constructed by @@ -69,7 +69,7 @@ class RegClass { public: RegClass(const Function *M, - const MachineRegClassInfo *MRC, + const TargetRegClassInfo *MRC, const ReservedColorListType *RCL = 0); inline void createInterferenceGraph() { IG.createGraph(); } diff --git a/lib/Target/SparcV9/SparcV9Internals.h b/lib/Target/SparcV9/SparcV9Internals.h index 0840522929..e5eaa0f222 100644 --- a/lib/Target/SparcV9/SparcV9Internals.h +++ b/lib/Target/SparcV9/SparcV9Internals.h @@ -9,10 +9,10 @@ #define SPARC_INTERNALS_H #include "llvm/Target/TargetMachine.h" -#include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Target/TargetSchedInfo.h" #include "llvm/Target/TargetFrameInfo.h" #include "llvm/Target/TargetCacheInfo.h" -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/Target/TargetOptInfo.h" #include "llvm/Type.h" #include <sys/types.h> @@ -211,11 +211,11 @@ struct UltraSparcInstrInfo : public MachineInstrInfo { //---------------------------------------------------------------------------- // class UltraSparcRegInfo // -// This class implements the virtual class MachineRegInfo for Sparc. +// This class implements the virtual class TargetRegInfo for Sparc. // //---------------------------------------------------------------------------- -class UltraSparcRegInfo : public MachineRegInfo { +class UltraSparcRegInfo : public TargetRegInfo { // The actual register classes in the Sparc // enum RegClassIDs { @@ -511,7 +511,7 @@ public: //--------------------------------------------------------------------------- -class UltraSparcSchedInfo: public MachineSchedInfo { +class UltraSparcSchedInfo: public TargetSchedInfo { public: UltraSparcSchedInfo(const TargetMachine &tgt); protected: @@ -734,8 +734,8 @@ public: UltraSparc(); virtual const MachineInstrInfo &getInstrInfo() const { return instrInfo; } - virtual const MachineSchedInfo &getSchedInfo() const { return schedInfo; } - virtual const MachineRegInfo &getRegInfo() const { return regInfo; } + virtual const TargetSchedInfo &getSchedInfo() const { return schedInfo; } + virtual const TargetRegInfo &getRegInfo() const { return regInfo; } virtual const TargetFrameInfo &getFrameInfo() const { return frameInfo; } virtual const TargetCacheInfo &getCacheInfo() const { return cacheInfo; } virtual const TargetOptInfo &getOptInfo() const { return optInfo; } diff --git a/lib/Target/SparcV9/SparcV9RegClassInfo.h b/lib/Target/SparcV9/SparcV9RegClassInfo.h index 467c3acf5f..a8a39eb86a 100644 --- a/lib/Target/SparcV9/SparcV9RegClassInfo.h +++ b/lib/Target/SparcV9/SparcV9RegClassInfo.h @@ -7,7 +7,7 @@ #ifndef SPARC_REG_CLASS_INFO_H #define SPARC_REG_CLASS_INFO_H -#include "llvm/Target/MachineRegInfo.h" +#include "llvm/Target/TargetRegInfo.h" #include "llvm/CodeGen/IGNode.h" //----------------------------------------------------------------------------- @@ -15,9 +15,9 @@ //----------------------------------------------------------------------------- -struct SparcIntRegClass : public MachineRegClassInfo { +struct SparcIntRegClass : public TargetRegClassInfo { SparcIntRegClass(unsigned ID) - : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { } + : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) { } void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const; @@ -73,12 +73,12 @@ struct SparcIntRegClass : public MachineRegClassInfo { // Float Register Class //----------------------------------------------------------------------------- -class SparcFloatRegClass : public MachineRegClassInfo { +class SparcFloatRegClass : public TargetRegClassInfo { int findFloatColor(const LiveRange *LR, unsigned Start, unsigned End, std::vector<bool> &IsColorUsedArr) const; public: SparcFloatRegClass(unsigned ID) - : MachineRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {} + : TargetRegClassInfo(ID, NumOfAvailRegs, NumOfAllRegs) {} void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const; @@ -119,9 +119,9 @@ public: // allocated for two names. //----------------------------------------------------------------------------- -struct SparcIntCCRegClass : public MachineRegClassInfo { +struct SparcIntCCRegClass : public TargetRegClassInfo { SparcIntCCRegClass(unsigned ID) - : MachineRegClassInfo(ID, 1, 2) { } + : TargetRegClassInfo(ID, 1, 2) { } void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const { if (IsColorUsedArr[0]) @@ -149,9 +149,9 @@ struct SparcIntCCRegClass : public MachineRegClassInfo { // Only 4 Float CC registers are available //----------------------------------------------------------------------------- -struct SparcFloatCCRegClass : public MachineRegClassInfo { +struct SparcFloatCCRegClass : public TargetRegClassInfo { SparcFloatCCRegClass(unsigned ID) - : MachineRegClassInfo(ID, 4, 4) { } + : TargetRegClassInfo(ID, 4, 4) { } void colorIGNode(IGNode *Node, std::vector<bool> &IsColorUsedArr) const { for(unsigned c = 0; c != 4; ++c) diff --git a/lib/Target/SparcV9/SparcV9RegInfo.cpp b/lib/Target/SparcV9/SparcV9RegInfo.cpp index 3caac417ca..e7889d2d50 100644 --- a/lib/Target/SparcV9/SparcV9RegInfo.cpp +++ b/lib/Target/SparcV9/SparcV9RegInfo.cpp @@ -25,7 +25,7 @@ using std::cerr; using std::vector; UltraSparcRegInfo::UltraSparcRegInfo(const UltraSparc &tgt) - : MachineRegInfo(tgt), NumOfIntArgRegs(6), + : TargetRegInfo(tgt), NumOfIntArgRegs(6), NumOfFloatArgRegs(32), InvalidRegNum(1000) { MachineRegClassArr.push_back(new SparcIntRegClass(IntRegClassID)); diff --git a/lib/Target/SparcV9/SparcV9SchedInfo.cpp b/lib/Target/SparcV9/SparcV9SchedInfo.cpp index 35a0526c92..92dc5830e5 100644 --- a/lib/Target/SparcV9/SparcV9SchedInfo.cpp +++ b/lib/Target/SparcV9/SparcV9SchedInfo.cpp @@ -700,12 +700,12 @@ static const InstrRUsageDelta SparcInstrUsageDeltas[] = { // Purpose: // Scheduling information for the UltraSPARC. // Primarily just initializes machine-dependent parameters in -// class MachineSchedInfo. +// class TargetSchedInfo. //--------------------------------------------------------------------------- /*ctor*/ UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt) - : MachineSchedInfo(tgt, + : TargetSchedInfo(tgt, (unsigned int) SPARC_NUM_SCHED_CLASSES, SparcRUsageDesc, SparcInstrUsageDeltas, @@ -733,8 +733,8 @@ UltraSparcSchedInfo::UltraSparcSchedInfo(const TargetMachine& tgt) void UltraSparcSchedInfo::initializeResources() { - // Compute MachineSchedInfo::instrRUsages and MachineSchedInfo::issueGaps - MachineSchedInfo::initializeResources(); + // Compute TargetSchedInfo::instrRUsages and TargetSchedInfo::issueGaps + TargetSchedInfo::initializeResources(); // Machine-dependent fixups go here. None for now. } diff --git a/lib/Target/TargetSchedInfo.cpp b/lib/Target/TargetSchedInfo.cpp index 185f01ec9e..d64652398a 100644 --- a/lib/Target/TargetSchedInfo.cpp +++ b/lib/Target/TargetSchedInfo.cpp @@ -5,7 +5,7 @@ // //===----------------------------------------------------------------------===// -#include "llvm/Target/MachineSchedInfo.h" +#include "llvm/Target/TargetSchedInfo.h" #include "llvm/Target/TargetMachine.h" resourceId_t MachineResource::nextId = 0; @@ -69,17 +69,17 @@ ComputeMinGap(const InstrRUsage &fromRU, //--------------------------------------------------------------------------- -// class MachineSchedInfo +// class TargetSchedInfo // Interface to machine description for instruction scheduling //--------------------------------------------------------------------------- -MachineSchedInfo::MachineSchedInfo(const TargetMachine& tgt, - int NumSchedClasses, - const InstrClassRUsage* ClassRUsages, - const InstrRUsageDelta* UsageDeltas, - const InstrIssueDelta* IssueDeltas, - unsigned int NumUsageDeltas, - unsigned int NumIssueDeltas) +TargetSchedInfo::TargetSchedInfo(const TargetMachine& tgt, + int NumSchedClasses, + const InstrClassRUsage* ClassRUsages, + const InstrRUsageDelta* UsageDeltas, + const InstrIssueDelta* IssueDeltas, + unsigned NumUsageDeltas, + unsigned NumIssueDeltas) : target(tgt), numSchedClasses(NumSchedClasses), mii(& tgt.getInstrInfo()), classRUsages(ClassRUsages), usageDeltas(UsageDeltas), @@ -88,7 +88,7 @@ MachineSchedInfo::MachineSchedInfo(const TargetMachine& tgt, {} void -MachineSchedInfo::initializeResources() +TargetSchedInfo::initializeResources() { assert(MAX_NUM_SLOTS >= (int)getMaxNumIssueTotal() && "Insufficient slots for static data! Increase MAX_NUM_SLOTS"); @@ -111,7 +111,7 @@ MachineSchedInfo::initializeResources() void -MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>& +TargetSchedInfo::computeInstrResources(const std::vector<InstrRUsage>& instrRUForClasses) { int numOpCodes = mii->getNumRealOpCodes(); @@ -141,7 +141,7 @@ MachineSchedInfo::computeInstrResources(const std::vector<InstrRUsage>& void -MachineSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>& +TargetSchedInfo::computeIssueGaps(const std::vector<InstrRUsage>& instrRUForClasses) { int numOpCodes = mii->getNumRealOpCodes(); diff --git a/lib/Target/X86/X86TargetMachine.h b/lib/Target/X86/X86TargetMachine.h index 9bf9a3779e..35a3b6a428 100644 --- a/lib/Target/X86/X86TargetMachine.h +++ b/lib/Target/X86/X86TargetMachine.h @@ -23,8 +23,8 @@ public: return &InstrInfo.getRegisterInfo(); } - virtual const MachineSchedInfo &getSchedInfo() const { abort(); } - virtual const MachineRegInfo &getRegInfo() const { abort(); } + virtual const TargetSchedInfo &getSchedInfo() const { abort(); } + virtual const TargetRegInfo &getRegInfo() const { abort(); } virtual const TargetCacheInfo &getCacheInfo() const { abort(); } virtual const TargetOptInfo &getOptInfo() const { abort(); } |