diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 12 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 16 |
2 files changed, 18 insertions, 10 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index 2e3362c609..219e1c704d 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -940,9 +940,11 @@ class AXI4ld<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, string asm, string cstr, list<dag> pattern> : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { + bits<4> p; bits<16> dsts; bits<4> Rn; bits<2> amode; + let Inst{31-28} = p; let Inst{27-25} = 0b100; let Inst{24-23} = amode; let Inst{22} = 0; // S bit @@ -954,10 +956,16 @@ class AXI4st<dag oops, dag iops, IndexMode im, Format f, InstrItinClass itin, string asm, string cstr, list<dag> pattern> : XI<oops, iops, AddrMode4, Size4Bytes, im, f, itin, asm, cstr, pattern> { + bits<4> p; bits<16> srcs; - let Inst{20} = 0; // L bit - let Inst{22} = 0; // S bit + bits<4> Rn; + bits<2> amode; + let Inst{31-28} = p; let Inst{27-25} = 0b100; + let Inst{24-23} = amode; + let Inst{22} = 0; // S bit + let Inst{20} = 0; // L bit + let Inst{19-16} = Rn; let Inst{15-0} = srcs; } diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index 5237a55255..c5db92f609 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -1185,8 +1185,6 @@ let isReturn = 1, isTerminator = 1, isBarrier = 1, mayLoad = 1, IndexModeUpd, LdStMulFrm, IIC_iLoad_mBr, "ldm${mode}${p}\t$Rn!, $dsts", "$Rn = $wb", []> { - bits<4> p; - let Inst{31-28} = p; let Inst{21} = 1; } @@ -1710,8 +1708,6 @@ def LDM : AXI4ld<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$dsts, variable_ops), IndexModeNone, LdStMulFrm, IIC_iLoad_m, "ldm${amode}${p}\t$Rn, $dsts", "", []> { - bits<4> p; - let Inst{31-28} = p; let Inst{21} = 0; } @@ -1720,8 +1716,6 @@ def LDM_UPD : AXI4ld<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, IndexModeUpd, LdStMulFrm, IIC_iLoad_mu, "ldm${amode}${p}\t$Rn!, $dsts", "$Rn = $wb", []> { - bits<4> p; - let Inst{31-28} = p; let Inst{21} = 1; } } // mayLoad, neverHasSideEffects, hasExtraDefRegAllocReq @@ -1731,13 +1725,19 @@ let mayStore = 1, neverHasSideEffects = 1, hasExtraSrcRegAllocReq = 1, def STM : AXI4st<(outs), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeNone, LdStMulFrm, IIC_iStore_m, - "stm${amode}${p}\t$Rn, $srcs", "", []>; + "stm${amode}${p}\t$Rn, $srcs", "", []> { + let Inst{21} = 0; +} def STM_UPD : AXI4st<(outs GPR:$wb), (ins GPR:$Rn, ldstm_mode:$amode, pred:$p, reglist:$srcs, variable_ops), IndexModeUpd, LdStMulFrm, IIC_iStore_mu, "stm${amode}${p}\t$Rn!, $srcs", - "$Rn = $wb", []>; + "$Rn = $wb", []> { + bits<4> p; + let Inst{31-28} = p; + let Inst{21} = 1; +} } // mayStore, neverHasSideEffects, hasExtraSrcRegAllocReq //===----------------------------------------------------------------------===// |