3 files changed, 5 insertions, 5 deletions
diff --git a/lib/CodeGen/LiveIntervalAnalysis.cpp b/lib/CodeGen/LiveIntervalAnalysis.cpp
index 83852ca8b9..57a73d2642 100644
--- a/lib/CodeGen/LiveIntervalAnalysis.cpp
+++ b/lib/CodeGen/LiveIntervalAnalysis.cpp
@@ -461,7 +461,7 @@ void LiveIntervals::handleVirtualRegisterDef(MachineBasicBlock *mbb,
       // If the kill happens after the definition, we have an intra-block
       // live range.
       if (killIdx > defIndex) {
-        assert(vi.AliveBlocks.empty() &&
+        assert(vi.AliveBlocks.none() &&
                "Shouldn't be alive across any blocks!");
         LiveRange LR(defIndex, killIdx, ValNum);
         interval.addRange(LR);
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 74d76c14fc..f862023e8f 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -789,7 +789,7 @@ bool RA::runOnMachineFunction(MachineFunction &Fn) {
   // is allocatable.  To handle this, we mark all unallocatable registers as
   // being pinned down, permanently.
   {
-    std::vector<bool> Allocable = RegInfo->getAllocatableSet(Fn);
+    BitVector Allocable = RegInfo->getAllocatableSet(Fn);
     for (unsigned i = 0, e = Allocable.size(); i != e; ++i)
       if (!Allocable[i])
         PhysRegsUsed[i] = -2;  // Mark the reg unallocable.
diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index 01295e802a..7caaae9d4f 100644
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -14,10 +14,10 @@
 #include "llvm/Target/TargetMachine.h"
 #include "llvm/Target/MRegisterInfo.h"
 #include "llvm/Target/TargetFrameInfo.h"
-
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineLocation.h"
+#include "llvm/ADT/BitVector.h"
 
 using namespace llvm;
 
@@ -34,8 +34,8 @@ MRegisterInfo::MRegisterInfo(const TargetRegisterDesc *D, unsigned NR,
 
 MRegisterInfo::~MRegisterInfo() {}
 
-std::vector<bool> MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
-  std::vector<bool> Allocatable(NumRegs);
+BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
+  BitVector Allocatable(NumRegs);
   for (MRegisterInfo::regclass_iterator I = regclass_begin(),
          E = regclass_end(); I != E; ++I) {
     const TargetRegisterClass *RC = *I;