diff options
Diffstat (limited to 'lib')
| -rw-r--r-- | lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp | 35 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 12 |
2 files changed, 42 insertions, 5 deletions
diff --git a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp index f1343886af..c3b2d4082c 100644 --- a/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp +++ b/lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp @@ -902,6 +902,18 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_ROUND(SDNode *N) { SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) { MVT RVT = N->getValueType(0); + + // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on + // PPC (the libcall is not available). FIXME: Do this in a less hacky way. + if (RVT == MVT::i32) { + assert(N->getOperand(0).getValueType() == MVT::ppcf128 && + "Logic only correct for ppcf128!"); + SDValue Res = DAG.getNode(ISD::FP_ROUND_INREG, MVT::ppcf128, + N->getOperand(0), DAG.getValueType(MVT::f64)); + Res = DAG.getNode(ISD::FP_ROUND, MVT::f64, Res, DAG.getIntPtrConstant(1)); + return DAG.getNode(ISD::FP_TO_SINT, MVT::i32, Res); + } + RTLIB::Libcall LC = RTLIB::getFPTOSINT(N->getOperand(0).getValueType(), RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_SINT!"); return MakeLibCall(LC, RVT, &N->getOperand(0), 1, false); @@ -909,6 +921,29 @@ SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_SINT(SDNode *N) { SDValue DAGTypeLegalizer::ExpandFloatOp_FP_TO_UINT(SDNode *N) { MVT RVT = N->getValueType(0); + + // Expand ppcf128 to i32 by hand for the benefit of llvm-gcc bootstrap on + // PPC (the libcall is not available). FIXME: Do this in a less hacky way. + if (RVT == MVT::i32) { + assert(N->getOperand(0).getValueType() == MVT::ppcf128 && + "Logic only correct for ppcf128!"); + const uint64_t TwoE31[] = {0x41e0000000000000LL, 0}; + APFloat APF = APFloat(APInt(128, 2, TwoE31)); + SDValue Tmp = DAG.getConstantFP(APF, MVT::ppcf128); + // X>=2^31 ? (int)(X-2^31)+0x80000000 : (int)X + // FIXME: generated code sucks. + return DAG.getNode(ISD::SELECT_CC, MVT::i32, N->getOperand(0), Tmp, + DAG.getNode(ISD::ADD, MVT::i32, + DAG.getNode(ISD::FP_TO_SINT, MVT::i32, + DAG.getNode(ISD::FSUB, + MVT::ppcf128, + N->getOperand(0), + Tmp)), + DAG.getConstant(0x80000000, MVT::i32)), + DAG.getNode(ISD::FP_TO_SINT, MVT::i32, N->getOperand(0)), + DAG.getCondCode(ISD::SETGE)); + } + RTLIB::Libcall LC = RTLIB::getFPTOUINT(N->getOperand(0).getValueType(), RVT); assert(LC != RTLIB::UNKNOWN_LIBCALL && "Unsupported FP_TO_UINT!"); return MakeLibCall(LC, N->getValueType(0), &N->getOperand(0), 1, false); diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index eb327dcdf2..5cf7eb28ef 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -2865,9 +2865,10 @@ SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op, assert(Op.getValueType() == MVT::ppcf128); SDNode *Node = Op.getNode(); assert(Node->getOperand(0).getValueType() == MVT::ppcf128); - assert(Node->getOperand(0).getNode()->getOpcode() == ISD::BUILD_PAIR); - SDValue Lo = Node->getOperand(0).getNode()->getOperand(0); - SDValue Hi = Node->getOperand(0).getNode()->getOperand(1); + SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, Node->getOperand(0), + DAG.getIntPtrConstant(0)); + SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, MVT::f64, Node->getOperand(0), + DAG.getIntPtrConstant(1)); // This sequence changes FPSCR to do round-to-zero, adds the two halves // of the long double, and puts FPSCR back the way it was. We do not @@ -2916,7 +2917,7 @@ SDValue PPCTargetLowering::LowerFP_ROUND_INREG(SDValue Op, // We know the low half is about to be thrown away, so just use something // convenient. - return DAG.getNode(ISD::BUILD_PAIR, Lo.getValueType(), FPreg, FPreg); + return DAG.getNode(ISD::BUILD_PAIR, MVT::ppcf128, FPreg, FPreg); } SDValue PPCTargetLowering::LowerSINT_TO_FP(SDValue Op, SelectionDAG &DAG) { @@ -3883,7 +3884,8 @@ SDValue PPCTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) { SDNode *PPCTargetLowering::ReplaceNodeResults(SDNode *N, SelectionDAG &DAG) { switch (N->getOpcode()) { - default: assert(0 && "Wasn't expecting to be able to lower this!"); + default: + return PPCTargetLowering::LowerOperation(SDValue (N, 0), DAG).getNode(); case ISD::FP_TO_SINT: { SDValue Res = LowerFP_TO_SINT(SDValue(N, 0), DAG); // Use MERGE_VALUES to drop the chain result value and get a node with one |