diff options
Diffstat (limited to 'lib')
32 files changed, 299 insertions, 270 deletions
diff --git a/lib/Target/Mips/Makefile b/lib/Target/Mips/Makefile index d16b066a62..bf77bdbcdc 100644 --- a/lib/Target/Mips/Makefile +++ b/lib/Target/Mips/Makefile @@ -1,11 +1,11 @@ -##===- lib/Target/Mips/Makefile ----------------------------*- Makefile -*-===## +##===- lib/Target/Mips/Makefile ---------------------------*- Makefile -*-===## # # The LLVM Compiler Infrastructure # # This file is distributed under the University of Illinois Open Source # License. See LICENSE.TXT for details. # -##===----------------------------------------------------------------------===## +##===---------------------------------------------------------------------===## LEVEL = ../../.. LIBRARYNAME = LLVMMipsCodeGen diff --git a/lib/Target/Mips/Mips.h b/lib/Target/Mips/Mips.h index 05b4c5a070..d9cdd4060a 100644 --- a/lib/Target/Mips/Mips.h +++ b/lib/Target/Mips/Mips.h @@ -1,16 +1,16 @@ -//===-- Mips.h - Top-level interface for Mips representation ----*- C++ -*-===// +//===-- Mips.h - Top-level interface for Mips representation ---*- C++ -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // This file contains the entry points for global functions defined in // the LLVM Mips back-end. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #ifndef TARGET_MIPS_H #define TARGET_MIPS_H diff --git a/lib/Target/Mips/Mips.td b/lib/Target/Mips/Mips.td index b79016d788..e971339a02 100644 --- a/lib/Target/Mips/Mips.td +++ b/lib/Target/Mips/Mips.td @@ -1,23 +1,23 @@ -//===- Mips.td - Describe the Mips Target Machine ----------*- tablegen -*-===// +//===- Mips.td - Describe the Mips Target Machine ---------*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // This is the top level entry point for the Mips target. -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Target-independent interfaces -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// include "llvm/Target/Target.td" -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Register File, Calling Conv, Instruction Descriptions -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// include "MipsRegisterInfo.td" include "MipsSchedule.td" @@ -26,16 +26,17 @@ include "MipsCallingConv.td" def MipsInstrInfo : InstrInfo; -//===----------------------------------------------------------------------===// -// Mips Subtarget features // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// +// Mips Subtarget features // +//===---------------------------------------------------------------------===// def FeatureGP64Bit : SubtargetFeature<"gp64", "IsGP64bit", "true", "General Purpose Registers are 64-bit wide.">; def FeatureFP64Bit : SubtargetFeature<"fp64", "IsFP64bit", "true", "Support 64-bit FP registers.">; def FeatureSingleFloat : SubtargetFeature<"single-float", "IsSingleFloat", - "true", "Only supports single precision float">; + "true", + "Only supports single precision float">; def FeatureO32 : SubtargetFeature<"o32", "MipsABI", "O32", "Enable o32 ABI">; def FeatureEABI : SubtargetFeature<"eabi", "MipsABI", "EABI", @@ -58,16 +59,16 @@ def FeatureMips1 : SubtargetFeature<"mips1", "MipsArchVersion", "Mips1", "Mips1 ISA Support">; def FeatureMips2 : SubtargetFeature<"mips2", "MipsArchVersion", "Mips2", "Mips2 ISA Support">; -def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", "Mips32", - "Mips32 ISA Support", +def FeatureMips32 : SubtargetFeature<"mips32", "MipsArchVersion", + "Mips32", "Mips32 ISA Support", [FeatureCondMov, FeatureBitCount]>; def FeatureMips32r2 : SubtargetFeature<"mips32r2", "MipsArchVersion", "Mips32r2", "Mips32r2 ISA Support", [FeatureMips32, FeatureSEInReg]>; -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Mips processors supported. -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// class Proc<string Name, list<SubtargetFeature> Features> : Processor<Name, MipsGenericItineraries, Features>; diff --git a/lib/Target/Mips/MipsAsmPrinter.cpp b/lib/Target/Mips/MipsAsmPrinter.cpp index 718110fcbf..6db64a504b 100644 --- a/lib/Target/Mips/MipsAsmPrinter.cpp +++ b/lib/Target/Mips/MipsAsmPrinter.cpp @@ -1,16 +1,16 @@ -//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer --------------------===// +//===-- MipsAsmPrinter.cpp - Mips LLVM assembly writer -------------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // This file contains a printer that converts from our internal representation // of machine-dependent LLVM code to GAS-format MIPS assembly language. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #define DEBUG_TYPE "mips-asm-printer" #include "Mips.h" @@ -68,7 +68,8 @@ namespace { const char *getCurrentABIString() const; void emitFrameDirective(); - void printInstruction(const MachineInstr *MI, raw_ostream &O); // autogen'd. + void printInstruction(const MachineInstr *MI, + raw_ostream &O); // autogen'd. void EmitInstruction(const MachineInstr *MI) { SmallString<128> Str; raw_svector_ostream OS(Str); @@ -77,7 +78,8 @@ namespace { } virtual void EmitFunctionBodyStart(); virtual void EmitFunctionBodyEnd(); - virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) const; + virtual bool isBlockOnlyReachableByFallthrough(const MachineBasicBlock + *MBB) const; static const char *getRegisterName(unsigned RegNo); virtual void EmitFunctionEntryLabel(); @@ -87,7 +89,7 @@ namespace { #include "MipsGenAsmWriter.inc" -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // Mips Asm Directives // @@ -116,11 +118,11 @@ namespace { // stack pointer subtration, the first register in the mask (RA) will be // saved at address 48-8=40. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Mask directives -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Create a bitmask with all callee saved registers for CPU or Floating Point // registers. For CPU registers consider RA, GP and FP for saving if necessary. @@ -172,9 +174,9 @@ void MipsAsmPrinter::printHex32(unsigned Value, raw_ostream &O) { O << utohexstr((Value & (0xF << (i*4))) >> (i*4)); } -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Frame and Set directives -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// /// Frame Directive void MipsAsmPrinter::emitFrameDirective() { @@ -236,8 +238,8 @@ void MipsAsmPrinter::EmitFunctionBodyEnd() { /// isBlockOnlyReachableByFallthough - Return true if the basic block has /// exactly one predecessor and the control transfer mechanism between /// the predecessor and this block is a fall-through. -bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock *MBB) - const { +bool MipsAsmPrinter::isBlockOnlyReachableByFallthrough(const MachineBasicBlock + *MBB) const { // The predecessor has to be immediately before this block. const MachineBasicBlock *Pred = *MBB->pred_begin(); @@ -390,7 +392,8 @@ void MipsAsmPrinter::EmitStartOfAsmFile(Module &M) { // FIXME: Use SwitchSection. // Tell the assembler which ABI we are using - OutStreamer.EmitRawText("\t.section .mdebug." + Twine(getCurrentABIString())); + OutStreamer.EmitRawText("\t.section .mdebug." + + Twine(getCurrentABIString())); // TODO: handle O64 ABI if (Subtarget->isABI_EABI()) { diff --git a/lib/Target/Mips/MipsCallingConv.td b/lib/Target/Mips/MipsCallingConv.td index 8e4b216404..63bc3fa5e5 100644 --- a/lib/Target/Mips/MipsCallingConv.td +++ b/lib/Target/Mips/MipsCallingConv.td @@ -1,21 +1,21 @@ -//===- MipsCallingConv.td - Calling Conventions for Mips ---*- tablegen -*-===// +//===- MipsCallingConv.td - Calling Conventions for Mips --*- tablegen -*-===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // This describes the calling conventions for Mips architecture. -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// /// CCIfSubtarget - Match if the current subtarget has a feature F. class CCIfSubtarget<string F, CCAction A>: CCIf<!strconcat("State.getTarget().getSubtarget<MipsSubtarget>().", F), A>; -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Mips O32 Calling Convention -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Only the return rules are defined here for O32. The rules for argument // passing are defined in MipsISelLowering.cpp. @@ -30,9 +30,9 @@ def RetCC_MipsO32 : CallingConv<[ CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0, D1]>>> ]>; -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Mips EABI Calling Convention -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// def CC_MipsEABI : CallingConv<[ // Promote i8/i16 arguments to i32. @@ -72,9 +72,9 @@ def RetCC_MipsEABI : CallingConv<[ CCIfType<[f64], CCIfSubtarget<"isNotSingleFloat()", CCAssignToReg<[D0]>>> ]>; -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Mips Calling Convention Dispatch -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// def CC_Mips : CallingConv<[ CCIfSubtarget<"isABI_EABI()", CCDelegateTo<CC_MipsEABI>> diff --git a/lib/Target/Mips/MipsDelaySlotFiller.cpp b/lib/Target/Mips/MipsDelaySlotFiller.cpp index b44a0af2d4..08d4948200 100644 --- a/lib/Target/Mips/MipsDelaySlotFiller.cpp +++ b/lib/Target/Mips/MipsDelaySlotFiller.cpp @@ -5,11 +5,11 @@ // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // Simple pass to fills delay slots with NOPs. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #define DEBUG_TYPE "delay-slot-filler" diff --git a/lib/Target/Mips/MipsExpandPseudo.cpp b/lib/Target/Mips/MipsExpandPseudo.cpp index 1e62af9dca..cf6105db65 100644 --- a/lib/Target/Mips/MipsExpandPseudo.cpp +++ b/lib/Target/Mips/MipsExpandPseudo.cpp @@ -1,16 +1,16 @@ -//===-- MipsExpandPseudo.cpp - Expand pseudo instructions ---------------------===// +//===-- MipsExpandPseudo.cpp - Expand pseudo instructions ---------------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // -// This pass expands pseudo instructions into target instructions after register -// allocation but before post-RA scheduling. +// This pass expands pseudo instructions into target instructions after +// register allocation but before post-RA scheduling. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #define DEBUG_TYPE "mips-expand-pseudo" @@ -42,7 +42,8 @@ namespace { private: void ExpandBuildPairF64(MachineBasicBlock&, MachineBasicBlock::iterator); - void ExpandExtractElementF64(MachineBasicBlock&, MachineBasicBlock::iterator); + void ExpandExtractElementF64(MachineBasicBlock&, + MachineBasicBlock::iterator); }; char MipsExpandPseudo::ID = 0; } // end of anonymous namespace @@ -85,7 +86,8 @@ bool MipsExpandPseudo::runOnMachineBasicBlock(MachineBasicBlock& MBB) { void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB, MachineBasicBlock::iterator I) { unsigned DstReg = I->getOperand(0).getReg(); - unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); + unsigned LoReg = I->getOperand(1).getReg(); + unsigned HiReg = I->getOperand(2).getReg(); const TargetInstrDesc& Mtc1Tdd = TII->get(Mips::MTC1); DebugLoc dl = I->getDebugLoc(); const unsigned* SubReg = @@ -98,7 +100,7 @@ void MipsExpandPseudo::ExpandBuildPairF64(MachineBasicBlock& MBB, } void MipsExpandPseudo::ExpandExtractElementF64(MachineBasicBlock& MBB, - MachineBasicBlock::iterator I) { + MachineBasicBlock::iterator I) { unsigned DstReg = I->getOperand(0).getReg(); unsigned SrcReg = I->getOperand(1).getReg(); unsigned N = I->getOperand(2).getImm(); diff --git a/lib/Target/Mips/MipsFrameLowering.cpp b/lib/Target/Mips/MipsFrameLowering.cpp index 66a3588a97..ded6e850f7 100644 --- a/lib/Target/Mips/MipsFrameLowering.cpp +++ b/lib/Target/Mips/MipsFrameLowering.cpp @@ -1,15 +1,15 @@ -//=======- MipsFrameLowering.cpp - Mips Frame Information ------*- C++ -*-====// +//=======- MipsFrameLowering.cpp - Mips Frame Information -----*- C++ -*-====// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // This file contains the Mips implementation of TargetFrameLowering class. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #include "MipsFrameLowering.h" #include "MipsInstrInfo.h" @@ -27,7 +27,7 @@ using namespace llvm; -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // Stack Frame Processing methods // +----------------------------+ @@ -77,11 +77,11 @@ using namespace llvm; // possible to detect those references and the offsets are adjusted to // their real location. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // hasFP - Return true if the specified function should have a dedicated frame -// pointer register. This is true if the function has variable sized allocas or -// if frame pointer elimination is disabled. +// pointer register. This is true if the function has variable sized allocas +// or if frame pointer elimination is disabled. bool MipsFrameLowering::hasFP(const MachineFunction &MF) const { const MachineFrameInfo *MFI = MF.getFrameInfo(); return DisableFramePointerElim(MF) || MFI->hasVarSizedObjects(); @@ -203,9 +203,8 @@ void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const { MipsFI->setFPUTopSavedRegOff(TopFPUSavedRegOff-StackOffset); } - -// expand pair of register and immediate if the immediate doesn't fit in the 16-bit -// offset field. +// expand pair of register and immediate if the immediate doesn't fit in the +// 16-bit offset field. // e.g. // if OrigImm = 0x10000, OrigReg = $sp: // generate the following sequence of instrs: @@ -216,7 +215,8 @@ void MipsFrameLowering::adjustMipsStackFrame(MachineFunction &MF) const { // return true static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm, unsigned& NewReg, int& NewImm, - MachineBasicBlock& MBB, MachineBasicBlock::iterator I) { + MachineBasicBlock& MBB, + MachineBasicBlock::iterator I) { // OrigImm fits in the 16-bit field if (OrigImm < 0x8000 && OrigImm >= -0x8000) { NewReg = OrigReg; @@ -228,12 +228,14 @@ static bool expandRegLargeImmPair(unsigned OrigReg, int OrigImm, const TargetInstrInfo *TII = MF->getTarget().getInstrInfo(); DebugLoc DL = I->getDebugLoc(); int ImmLo = OrigImm & 0xffff; - int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) + ((OrigImm & 0x8000) != 0); + int ImmHi = (((unsigned)OrigImm & 0xffff0000) >> 16) + + ((OrigImm & 0x8000) != 0); // FIXME: change this when mips goes MC". BuildMI(MBB, I, DL, TII->get(Mips::NOAT)); BuildMI(MBB, I, DL, TII->get(Mips::LUi), Mips::AT).addImm(ImmHi); - BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg).addReg(Mips::AT); + BuildMI(MBB, I, DL, TII->get(Mips::ADDu), Mips::AT).addReg(OrigReg) + .addReg(Mips::AT); NewReg = Mips::AT; NewImm = ImmLo; diff --git a/lib/Target/Mips/MipsFrameLowering.h b/lib/Target/Mips/MipsFrameLowering.h index 34647df4f3..590071c07a 100644 --- a/lib/Target/Mips/MipsFrameLowering.h +++ b/lib/Target/Mips/MipsFrameLowering.h @@ -1,15 +1,15 @@ -//==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*---===// +//==--- MipsFrameLowering.h - Define frame lowering for Mips --*- C++ -*--===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #ifndef MIPS_FRAMEINFO_H #define MIPS_FRAMEINFO_H diff --git a/lib/Target/Mips/MipsISelDAGToDAG.cpp b/lib/Target/Mips/MipsISelDAGToDAG.cpp index 0382964fe9..ab1737f398 100644 --- a/lib/Target/Mips/MipsISelDAGToDAG.cpp +++ b/lib/Target/Mips/MipsISelDAGToDAG.cpp @@ -1,15 +1,15 @@ -//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips --------===// +//===-- MipsISelDAGToDAG.cpp - A dag to dag inst selector for Mips -------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // This file defines an instruction selector for the MIPS target. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #define DEBUG_TYPE "mips-isel" #include "Mips.h" @@ -34,14 +34,14 @@ #include "llvm/Support/raw_ostream.h" using namespace llvm; -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Instruction Selector Implementation -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // MipsDAGToDAGISel - MIPS specific code to select MIPS machine // instructions for SelectionDAG operations. -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// namespace { class MipsDAGToDAGISel : public SelectionDAGISel { diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index a4fc859c4a..fef720c80f 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -1,16 +1,16 @@ -//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation -----------===// +//===-- MipsISelLowering.cpp - Mips DAG Lowering Implementation ----------===// // // The LLVM Compiler Infrastructure // // This file is distributed under the University of Illinois Open Source // License. See LICENSE.TXT for details. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // // This file defines the interfaces that Mips uses to lower LLVM code into a // selection DAG. // -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// #define DEBUG_TYPE "mips-lower" #include "MipsISelLowering.h" @@ -221,8 +221,8 @@ static bool SelectMadd(SDNode* ADDENode, SelectionDAG* CurDAG) { // Transform this to a MADD only if ADDENode and ADDCNode are the only users // of the values of MultNode, in which case MultNode will be removed in later // phases. - // If there exist users other than ADDENode or ADDCNode, this function returns - // here, which will result in MultNode being mapped to a single MULT + // If there exist users other than ADDENode or ADDCNode, this function + // returns here, which will result in MultNode being mapped to a single MULT // instruction node rather than a pair of MULT and MADD instructions being // produced. if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) @@ -295,8 +295,8 @@ static bool SelectMsub(SDNode* SUBENode, SelectionDAG* CurDAG) { // Transform this to a MSUB only if SUBENode and SUBCNode are the only users // of the values of MultNode, in which case MultNode will be removed in later // phases. - // If there exist users other than SUBENode or SUBCNode, this function returns - // here, which will result in MultNode being mapped to a single MULT + // If there exist users other than SUBENode or SUBCNode, this function + // returns here, which will result in MultNode being mapped to a single MULT // instruction node rather than a pair of MULT and MSUB instructions being // produced. if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) @@ -444,8 +444,8 @@ static SDValue CreateFPCmp(SelectionDAG& DAG, const SDValue& Op) { SDValue RHS = Op.getOperand(1); DebugLoc dl = Op.getDebugLoc(); - // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of node - // if necessary. + // Assume the 3rd operand is a CondCodeSDNode. Add code to check the type of + // node if necessary. ISD::CondCode CC = cast<CondCodeSDNode>(Op.getOperand(2))->get(); return DAG.getNode(MipsISD::FPCmp, dl, MVT::Glue, LHS, RHS, @@ -520,9 +520,9 @@ LowerOperation(SDValue Op, SelectionDAG &DAG) const return SDValue(); } -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Lower helper functions -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // AddLiveIn - This helper function adds the specified physical register to the // MachineFunction as a live in value. It also creates a corresponding @@ -653,9 +653,9 @@ MipsTargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, return BB; } -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// // Misc Lower Operation implementation -//===----------------------------------------------------------------------===// +//===---------------------------------------------------------------------===// SDValue MipsTargetLowering:: LowerFP_TO_SINT(SDValue Op, SelectionDAG &DAG) const @@ -851,7 +851,8 @@ LowerJumpTable(SDValue Op, SelectionDAG &DAG) const MachinePointerInfo(), false, false, 0); - SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, MipsII::MO_ABS_LO); + SDValue JTILo = DAG.getTargetJumpTable(JT->getIndex(), PtrVT, + MipsII::MO_ABS_LO); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, JTILo); ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); @@ -879,9 +880,11 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const if (getTargetMachine().getRelocationModel() != Reloc::PIC_) { SDValue CPHi = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), - N->getOffset(), MipsII::MO_ABS_HI); + N->getOffset(), + MipsII::MO_ABS_HI); SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), - N->getOffset(), MipsII::MO_ABS_LO); + N->getOffset(), + MipsII::MO_ABS_LO); SDValue HiPart = DAG.getNode(MipsISD::Hi, dl, MVT::i32, CPHi); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, HiPart, Lo); @@ -892,7 +895,8 @@ LowerConstantPool(SDValue Op, SelectionDAG &DAG) const CP, MachinePointerInfo::getConstantPool(), false, false, 0); SDValue CPLo = DAG.getTargetConstantPool(C, MVT::i32, N->getAlignment(), - N->getOffset(), MipsII::MO_ABS_LO); + N->getOffset(), + MipsII::MO_ABS_LO); SDValue Lo = DAG.getNode(MipsISD::Lo, dl, MVT::i32, CPLo); ResNode = DAG.getNode(ISD::ADD, dl, MVT::i32, Load, Lo); } @@ -916,13 +920,13 @@ SDValue MipsTargetLowering::LowerVASTART(SDValue Op, SelectionDAG &DAG) const { false, false, 0); } |