diff options
Diffstat (limited to 'lib/Target')
| -rw-r--r-- | lib/Target/Sparc/SparcISelDAGToDAG.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp | 10 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 3 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.h | 3 |
4 files changed, 10 insertions, 16 deletions
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp index 099c2e5ed6..a9c4950614 100644 --- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp +++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp @@ -62,8 +62,7 @@ namespace { /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op, - uint64_t Mask, - MVIZFnPtr MVIZ) const; + uint64_t Mask) const; virtual std::vector<SDOperand> LowerArguments(Function &F, SelectionDAG &DAG); @@ -203,16 +202,15 @@ const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const { /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. bool SparcV8TargetLowering:: -isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask, - MVIZFnPtr MVIZ) const { +isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const { switch (Op.getOpcode()) { default: return false; case V8ISD::SELECT_ICC: case V8ISD::SELECT_FCC: assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!"); // These operations are masked zero if both the left and the right are zero. - return MVIZ(Op.getOperand(0), Mask, *this) && - MVIZ(Op.getOperand(1), Mask, *this); + return MaskedValueIsZero(Op.getOperand(0), Mask) && + MaskedValueIsZero(Op.getOperand(1), Mask); } } diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp index 099c2e5ed6..a9c4950614 100644 --- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp +++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp @@ -62,8 +62,7 @@ namespace { /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op, - uint64_t Mask, - MVIZFnPtr MVIZ) const; + uint64_t Mask) const; virtual std::vector<SDOperand> LowerArguments(Function &F, SelectionDAG &DAG); @@ -203,16 +202,15 @@ const char *SparcV8TargetLowering::getTargetNodeName(unsigned Opcode) const { /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. bool SparcV8TargetLowering:: -isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask, - MVIZFnPtr MVIZ) const { +isMaskedValueZeroForTargetNode(const SDOperand &Op, uint64_t Mask) const { switch (Op.getOpcode()) { default: return false; case V8ISD::SELECT_ICC: case V8ISD::SELECT_FCC: assert(MVT::isInteger(Op.getValueType()) && "Not an integer select!"); // These operations are masked zero if both the left and the right are zero. - return MVIZ(Op.getOperand(0), Mask, *this) && - MVIZ(Op.getOperand(1), Mask, *this); + return MaskedValueIsZero(Op.getOperand(0), Mask) && + MaskedValueIsZero(Op.getOperand(1), Mask); } } diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 5c4b9f8c71..9503bc13c4 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -1932,8 +1932,7 @@ const char *X86TargetLowering::getTargetNodeName(unsigned Opcode) const { } bool X86TargetLowering::isMaskedValueZeroForTargetNode(const SDOperand &Op, - uint64_t Mask, - MVIZFnPtr MVIZ) const { + uint64_t Mask) const { unsigned Opc = Op.getOpcode(); diff --git a/lib/Target/X86/X86ISelLowering.h b/lib/Target/X86/X86ISelLowering.h index 99d1442cd4..fc601702d5 100644 --- a/lib/Target/X86/X86ISelLowering.h +++ b/lib/Target/X86/X86ISelLowering.h @@ -208,8 +208,7 @@ namespace llvm { /// be zero. Op is expected to be a target specific node. Used by DAG /// combiner. virtual bool isMaskedValueZeroForTargetNode(const SDOperand &Op, - uint64_t Mask, - MVIZFnPtr MVIZ) const; + uint64_t Mask) const; SDOperand getReturnAddressFrameIndex(SelectionDAG &DAG); |