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-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp20
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp24
-rw-r--r--lib/Target/Alpha/AlphaISelDAGToDAG.cpp8
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp22
-rw-r--r--lib/Target/CellSPU/SPUISelDAGToDAG.cpp6
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp70
-rw-r--r--lib/Target/CellSPU/SPUOperands.td46
-rw-r--r--lib/Target/IA64/IA64ISelDAGToDAG.cpp6
-rw-r--r--lib/Target/IA64/IA64ISelLowering.cpp8
-rw-r--r--lib/Target/Mips/MipsISelDAGToDAG.cpp8
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp18
-rw-r--r--lib/Target/PIC16/PIC16ISelDAGToDAG.cpp12
-rw-r--r--lib/Target/PIC16/PIC16ISelLowering.cpp16
-rw-r--r--lib/Target/PowerPC/PPCISelDAGToDAG.cpp24
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp144
-rw-r--r--lib/Target/PowerPC/PPCInstrAltivec.td6
-rw-r--r--lib/Target/Sparc/SparcISelDAGToDAG.cpp4
-rw-r--r--lib/Target/Sparc/SparcISelLowering.cpp16
-rw-r--r--lib/Target/X86/X86ISelDAGToDAG.cpp144
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp216
20 files changed, 409 insertions, 409 deletions
diff --git a/lib/Target/ARM/ARMISelDAGToDAG.cpp b/lib/Target/ARM/ARMISelDAGToDAG.cpp
index 498729f985..609a62ae76 100644
--- a/lib/Target/ARM/ARMISelDAGToDAG.cpp
+++ b/lib/Target/ARM/ARMISelDAGToDAG.cpp
@@ -529,7 +529,7 @@ static inline SDValue getAL(SelectionDAG *CurDAG) {
SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
- SDNode *N = Op.Val;
+ SDNode *N = Op.getNode();
if (N->isMachineOpcode())
return NULL; // Already selected.
@@ -729,11 +729,11 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue Ops[] = { N1, Tmp2, N3, Chain, InFlag };
SDNode *ResNode = CurDAG->getTargetNode(Opc, MVT::Other, MVT::Flag, Ops, 5);
Chain = SDValue(ResNode, 0);
- if (Op.Val->getNumValues() == 2) {
+ if (Op.getNode()->getNumValues() == 2) {
InFlag = SDValue(ResNode, 1);
- ReplaceUses(SDValue(Op.Val, 1), InFlag);
+ ReplaceUses(SDValue(Op.getNode(), 1), InFlag);
}
- ReplaceUses(SDValue(Op.Val, 0), SDValue(Chain.Val, Chain.getResNo()));
+ ReplaceUses(SDValue(Op.getNode(), 0), SDValue(Chain.getNode(), Chain.getResNo()));
return NULL;
}
case ARMISD::CMOV: {
@@ -763,7 +763,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDValue Ops[] = { N0, CPTmp0, CPTmp1, CPTmp2, Tmp2, N3, InFlag };
- return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCs, MVT::i32, Ops, 7);
+ return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCs, MVT::i32, Ops, 7);
}
// Pattern: (ARMcmov:i32 GPR:i32:$false,
@@ -774,16 +774,16 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
// Pattern complexity = 10 cost = 1 size = 0
if (VT == MVT::i32 &&
N3.getOpcode() == ISD::Constant &&
- Predicate_so_imm(N3.Val)) {
+ Predicate_so_imm(N3.getNode())) {
AddToISelQueue(N0);
AddToISelQueue(InFlag);
SDValue Tmp1 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N1)->getValue()), MVT::i32);
- Tmp1 = Transform_so_imm_XFORM(Tmp1.Val);
+ Tmp1 = Transform_so_imm_XFORM(Tmp1.getNode());
SDValue Tmp2 = CurDAG->getTargetConstant(((unsigned)
cast<ConstantSDNode>(N2)->getValue()), MVT::i32);
SDValue Ops[] = { N0, Tmp1, Tmp2, N3, InFlag };
- return CurDAG->SelectNodeTo(Op.Val, ARM::MOVCCi, MVT::i32, Ops, 5);
+ return CurDAG->SelectNodeTo(Op.getNode(), ARM::MOVCCi, MVT::i32, Ops, 5);
}
// Pattern: (ARMcmov:i32 GPR:i32:$false, GPR:i32:$true, (imm:i32):$cc)
@@ -815,7 +815,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
Opc = ARM::FCPYDcc;
break;
}
- return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
+ return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
}
case ARMISD::CNEG: {
MVT VT = Op.getValueType();
@@ -844,7 +844,7 @@ SDNode *ARMDAGToDAGISel::Select(SDValue Op) {
Opc = ARM::FNEGDcc;
break;
}
- return CurDAG->SelectNodeTo(Op.Val, Opc, VT, Ops, 5);
+ return CurDAG->SelectNodeTo(Op.getNode(), Opc, VT, Ops, 5);
}
}
return SelectCode(Op);
diff --git a/lib/Target/ARM/ARMISelLowering.cpp b/lib/Target/ARM/ARMISelLowering.cpp
index c853a32125..b827a23919 100644
--- a/lib/Target/ARM/ARMISelLowering.cpp
+++ b/lib/Target/ARM/ARMISelLowering.cpp
@@ -400,7 +400,7 @@ HowToPassArgument(MVT ObjectVT, unsigned NumGPRs,
/// ARMISD:CALL <- callseq_end chain. Also add input and output parameter
/// nodes.
SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
- MVT RetVT= Op.Val->getValueType(0);
+ MVT RetVT= Op.getNode()->getValueType(0);
SDValue Chain = Op.getOperand(0);
unsigned CallConv = cast<ConstantSDNode>(Op.getOperand(1))->getValue();
assert((CallConv == CallingConv::C ||
@@ -597,7 +597,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
- if (InFlag.Val)
+ if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
@@ -621,7 +621,7 @@ SDValue ARMTargetLowering::LowerCALL(SDValue Op, SelectionDAG &DAG) {
case MVT::i32:
Chain = DAG.getCopyFromReg(Chain, ARM::R0, MVT::i32, InFlag).getValue(1);
ResultVals.push_back(Chain.getValue(0));
- if (Op.Val->getValueType(1) == MVT::i32) {
+ if (Op.getNode()->getValueType(1) == MVT::i32) {
// Returns a i64 value.
Chain = DAG.getCopyFromReg(Chain, ARM::R1, MVT::i32,
Chain.getValue(2)).getValue(1);
@@ -981,7 +981,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
unsigned ArgOffset = 0; // Frame mechanisms handle retaddr slot
unsigned NumGPRs = 0; // GPRs used for parameter passing.
- unsigned NumArgs = Op.Val->getNumValues()-1;
+ unsigned NumArgs = Op.getNode()->getNumValues()-1;
for (unsigned ArgNo = 0; ArgNo < NumArgs; ++ArgNo)
ArgValues.push_back(LowerFORMAL_ARGUMENT(Op, DAG, ArgNo,
NumGPRs, ArgOffset));
@@ -1029,7 +1029,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+ return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
ArgValues.size());
}
@@ -1037,7 +1037,7 @@ ARMTargetLowering::LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG) {
static bool isFloatingPointZero(SDValue Op) {
if (ConstantFPSDNode *CFP = dyn_cast<ConstantFPSDNode>(Op))
return CFP->getValueAPF().isPosZero();
- else if (ISD::isEXTLoad(Op.Val) || ISD::isNON_EXTLoad(Op.Val)) {
+ else if (ISD::isEXTLoad(Op.getNode()) || ISD::isNON_EXTLoad(Op.getNode())) {
// Maybe this has already been legalized into the constant pool?
if (Op.getOperand(1).getOpcode() == ARMISD::Wrapper) {
SDValue WrapperOp = Op.getOperand(1).getOperand(0);
@@ -1058,7 +1058,7 @@ static bool isLegalCmpImmediate(unsigned C, bool isThumb) {
/// the given operands.
static SDValue getARMCmp(SDValue LHS, SDValue RHS, ISD::CondCode CC,
SDValue &ARMCC, SelectionDAG &DAG, bool isThumb) {
- if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.Val)) {
+ if (ConstantSDNode *RHSC = dyn_cast<ConstantSDNode>(RHS.getNode())) {
unsigned C = RHSC->getValue();
if (!isLegalCmpImmediate(C, isThumb)) {
// Constant does not fit, try adjusting it by one?
@@ -1362,7 +1362,7 @@ static SDNode *ExpandBIT_CONVERT(SDNode *N, SelectionDAG &DAG) {
&Op, 1);
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).Val;
+ return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Cvt, Cvt.getValue(1)).getNode();
}
static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
@@ -1393,7 +1393,7 @@ static SDNode *ExpandSRx(SDNode *N, SelectionDAG &DAG, const ARMSubtarget *ST) {
Lo = DAG.getNode(ARMISD::RRX, MVT::i32, Lo, Hi.getValue(1));
// Merge the pieces into a single i64 value.
- return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).Val;
+ return DAG.getNode(ISD::BUILD_PAIR, MVT::i64, Lo, Hi).getNode();
}
@@ -1424,9 +1424,9 @@ SDValue ARMTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
// FIXME: Remove these when LegalizeDAGTypes lands.
- case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.Val, DAG), 0);
+ case ISD::BIT_CONVERT: return SDValue(ExpandBIT_CONVERT(Op.getNode(), DAG), 0);
case ISD::SRL:
- case ISD::SRA: return SDValue(ExpandSRx(Op.Val, DAG,Subtarget),0);
+ case ISD::SRA: return SDValue(ExpandSRx(Op.getNode(), DAG,Subtarget),0);
}
return SDValue();
}
@@ -1734,7 +1734,7 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
return false;
bool isInc;
- bool isLegal = getIndexedAddressParts(Ptr.Val, VT, isSEXTLoad, Base, Offset,
+ bool isLegal = getIndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base, Offset,
isInc, DAG);
if (isLegal) {
AM = isInc ? ISD::PRE_INC : ISD::PRE_DEC;
diff --git a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
index ce6afc3b81..5487eaa964 100644
--- a/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
+++ b/lib/Target/Alpha/AlphaISelDAGToDAG.cpp
@@ -75,7 +75,7 @@ namespace {
Result |= 1 << i;
if (((Constant >> 8*i) & 0xFF) == 0xFF) {
// If the entire byte is set, zapnot the byte.
- } else if (LHS.Val == 0) {
+ } else if (LHS.getNode() == 0) {
// Otherwise, if the mask was previously validated, we know its okay
// to zapnot this entire byte even though all the bits aren't set.
} else {
@@ -242,7 +242,7 @@ void AlphaDAGToDAGISel::InstructionSelect() {
// Select - Convert the specified operand from a target-independent to a
// target-specific node if it hasn't already been changed.
SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
- SDNode *N = Op.Val;
+ SDNode *N = Op.getNode();
if (N->isMachineOpcode()) {
return NULL; // Already selected.
}
@@ -345,7 +345,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
}
case ISD::SETCC:
- if (N->getOperand(0).Val->getValueType(0).isFloatingPoint()) {
+ if (N->getOperand(0).getNode()->getValueType(0).isFloatingPoint()) {
ISD::CondCode CC = cast<CondCodeSDNode>(N->getOperand(2))->get();
unsigned Opc = Alpha::WTF;
@@ -460,7 +460,7 @@ SDNode *AlphaDAGToDAGISel::Select(SDValue Op) {
void AlphaDAGToDAGISel::SelectCALL(SDValue Op) {
//TODO: add flag stuff to prevent nondeturministic breakage!
- SDNode *N = Op.Val;
+ SDNode *N = Op.getNode();
SDValue Chain = N->getOperand(0);
SDValue Addr = N->getOperand(1);
SDValue InFlag(0,0); // Null incoming flag value.
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index 5128646489..7beea3b76a 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -215,7 +215,7 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
unsigned args_float[] = {
Alpha::F16, Alpha::F17, Alpha::F18, Alpha::F19, Alpha::F20, Alpha::F21};
- for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
+ for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
SDValue argt;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
SDValue ArgVal;
@@ -255,7 +255,7 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
// If the functions takes variable number of arguments, copy all regs to stack
bool isVarArg = cast<ConstantSDNode>(Op.getOperand(2))->getValue() != 0;
if (isVarArg) {
- VarArgsOffset = (Op.Val->getNumValues()-1) * 8;
+ VarArgsOffset = (Op.getNode()->getNumValues()-1) * 8;
std::vector<SDValue> LS;
for (int i = 0; i < 6; ++i) {
if (TargetRegisterInfo::isPhysicalRegister(args_int[i]))
@@ -281,7 +281,7 @@ static SDValue LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG,
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+ return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
ArgValues.size());
}
@@ -491,10 +491,10 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
case ISD::SREM:
//Expand only on constant case
if (Op.getOperand(1).getOpcode() == ISD::Constant) {
- MVT VT = Op.Val->getValueType(0);
- SDValue Tmp1 = Op.Val->getOpcode() == ISD::UREM ?
- BuildUDIV(Op.Val, DAG, NULL) :
- BuildSDIV(Op.Val, DAG, NULL);
+ MVT VT = Op.getNode()->getValueType(0);
+ SDValue Tmp1 = Op.getNode()->getOpcode() == ISD::UREM ?
+ BuildUDIV(Op.getNode(), DAG, NULL) :
+ BuildSDIV(Op.getNode(), DAG, NULL);
Tmp1 = DAG.getNode(ISD::MUL, VT, Tmp1, Op.getOperand(1));
Tmp1 = DAG.getNode(ISD::SUB, VT, Op.getOperand(0), Tmp1);
return Tmp1;
@@ -504,8 +504,8 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
case ISD::UDIV:
if (Op.getValueType().isInteger()) {
if (Op.getOperand(1).getOpcode() == ISD::Constant)
- return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.Val, DAG, NULL)
- : BuildUDIV(Op.Val, DAG, NULL);
+ return Op.getOpcode() == ISD::SDIV ? BuildSDIV(Op.getNode(), DAG, NULL)
+ : BuildUDIV(Op.getNode(), DAG, NULL);
const char* opstr = 0;
switch (Op.getOpcode()) {
case ISD::UREM: opstr = "__remqu"; break;
@@ -522,7 +522,7 @@ SDValue AlphaTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) {
case ISD::VAARG: {
SDValue Chain, DataPtr;
- LowerVAARG(Op.Val, Chain, DataPtr, DAG);
+ LowerVAARG(Op.getNode(), Chain, DataPtr, DAG);
SDValue Result;
if (Op.getValueType() == MVT::i32)
@@ -578,7 +578,7 @@ SDNode *AlphaTargetLowering::ReplaceNodeResults(SDNode *N,
SDValue Chain, DataPtr;
LowerVAARG(N, Chain, DataPtr, DAG);
- return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).Val;
+ return DAG.getLoad(N->getValueType(0), Chain, DataPtr, NULL, 0).getNode();
}
diff --git a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
index c2a3e3a8df..9bf7c994d4 100644
--- a/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
+++ b/lib/Target/CellSPU/SPUISelDAGToDAG.cpp
@@ -579,7 +579,7 @@ SPUDAGToDAGISel::SelectXFormAddr(SDValue Op, SDValue N, SDValue &Base,
*/
SDNode *
SPUDAGToDAGISel::Select(SDValue Op) {
- SDNode *N = Op.Val;
+ SDNode *N = Op.getNode();
unsigned Opc = N->getOpcode();
int n_ops = -1;
unsigned NewOpc;
@@ -669,9 +669,9 @@ SPUDAGToDAGISel::Select(SDValue Op) {
MVT VT = Op.getValueType();
DEBUG(cerr << "CellSPU: IndirectAddr(LDRESULT, imm):\nOp0 = ");
- DEBUG(Op.getOperand(0).Val->dump(CurDAG));
+ DEBUG(Op.getOperand(0).getNode()->dump(CurDAG));
DEBUG(cerr << "\nOp1 = ");
- DEBUG(Op.getOperand(1).Val->dump(CurDAG));
+ DEBUG(Op.getOperand(1).getNode()->dump(CurDAG));
DEBUG(cerr << "\n");
if (Op1.getOpcode() == ISD::Constant) {
diff --git a/lib/Target/CellSPU/SPUISelLowering.cpp b/lib/Target/CellSPU/SPUISelLowering.cpp
index 4baadedd0f..4e93ea14b1 100644
--- a/lib/Target/CellSPU/SPUISelLowering.cpp
+++ b/lib/Target/CellSPU/SPUISelLowering.cpp
@@ -503,7 +503,7 @@ AlignedLoad(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST,
SDValue chain = LSN->getChain();
if (basePtr.getOpcode() == ISD::ADD) {
- SDValue Op1 = basePtr.Val->getOperand(1);
+ SDValue Op1 = basePtr.getNode()->getOperand(1);
if (Op1.getOpcode() == ISD::Constant || Op1.getOpcode() == ISD::TargetConstant) {
const ConstantSDNode *CN = cast<ConstantSDNode>(basePtr.getOperand(1));
@@ -579,7 +579,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
LoadSDNode *LN = cast<LoadSDNode>(Op);
SDValue the_chain = LN->getChain();
MVT VT = LN->getMemoryVT();
- MVT OpVT = Op.Val->getValueType(0);
+ MVT OpVT = Op.getNode()->getValueType(0);
ISD::LoadExtType ExtType = LN->getExtensionType();
unsigned alignment = LN->getAlignment();
SDValue Ops[8];
@@ -591,7 +591,7 @@ LowerLOAD(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
SDValue result =
AlignedLoad(Op, DAG, ST, LN,alignment, offset, rotamt, VT, was16aligned);
- if (result.Val == 0)
+ if (result.getNode() == 0)
return result;
the_chain = result.getValue(1);
@@ -708,7 +708,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
AlignedLoad(Op, DAG, ST, SN, alignment,
chunk_offset, slot_offset, VT, was16aligned);
- if (alignLoadVec.Val == 0)
+ if (alignLoadVec.getNode() == 0)
return alignLoadVec;
LoadSDNode *LN = cast<LoadSDNode>(alignLoadVec);
@@ -736,7 +736,7 @@ LowerSTORE(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
// Otherwise generate a D-form address with the slot offset relative
// to the stack pointer, which is always aligned.
DEBUG(cerr << "CellSPU LowerSTORE: basePtr = ");
- DEBUG(basePtr.Val->dump(&DAG));
+ DEBUG(basePtr.getNode()->dump(&DAG));
DEBUG(cerr << "\n");
if (basePtr.getOpcode() == SPUISD::IndirectAddr ||
@@ -859,7 +859,7 @@ LowerGlobalAddress(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
static SDValue
LowerConstant(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
- ConstantSDNode *CN = cast<ConstantSDNode>(Op.Val);
+ ConstantSDNode *CN = cast<ConstantSDNode>(Op.getNode());
if (VT == MVT::i64) {
SDValue T = DAG.getConstant(CN->getValue(), MVT::i64);
@@ -880,7 +880,7 @@ LowerConstant(SDValue Op, SelectionDAG &DAG) {
static SDValue
LowerConstantFP(SDValue Op, SelectionDAG &DAG) {
MVT VT = Op.getValueType();
- ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.Val);
+ ConstantFPSDNode *FP = cast<ConstantFPSDNode>(Op.getNode());
assert((FP != 0) &&
"LowerConstantFP: Node is not ConstantFPSDNode");
@@ -932,7 +932,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
MVT PtrVT = DAG.getTargetLoweringInfo().getPointerTy();
// Add DAG nodes to load the arguments or copy them out of registers.
- for (unsigned ArgNo = 0, e = Op.Val->getNumValues()-1; ArgNo != e; ++ArgNo) {
+ for (unsigned ArgNo = 0, e = Op.getNode()->getNumValues()-1; ArgNo != e; ++ArgNo) {
SDValue ArgVal;
bool needsLoad = false;
MVT ObjectVT = Op.getValue(ArgNo).getValueType();
@@ -1061,7 +1061,7 @@ LowerFORMAL_ARGUMENTS(SDValue Op, SelectionDAG &DAG, int &VarArgsFrameIndex)
ArgValues.push_back(Root);
// Return the new list of results.
- return DAG.getMergeValues(Op.Val->getVTList(), &ArgValues[0],
+ return DAG.getMergeValues(Op.getNode()->getVTList(), &ArgValues[0],
ArgValues.size());
}
@@ -1076,7 +1076,7 @@ static SDNode *isLSAAddress(SDValue Op, SelectionDAG &DAG) {
(Addr << 14 >> 14) != Addr)
return 0; // Top 14 bits have to be sext of immediate.
- return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).Val;
+ return DAG.getConstant((int)C->getValue() >> 2, MVT::i32).getNode();
}
static
@@ -1226,7 +1226,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
Ops.push_back(DAG.getRegister(RegsToPass[i].first,
RegsToPass[i].second.getValueType()));
- if (InFlag.Val)
+ if (InFlag.getNode())
Ops.push_back(InFlag);
// Returns a chain and a flag for retval copy to use.
Chain = DAG.getNode(CallOpc, DAG.getVTList(MVT::Other, MVT::Flag),
@@ -1237,18 +1237,18 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
DAG.getConstant(NumStackBytes, PtrVT),
DAG.getConstant(0, PtrVT),
InFlag);
- if (Op.Val->getValueType(0) != MVT::Other)
+ if (Op.getNode()->getValueType(0) != MVT::Other)
InFlag = Chain.getValue(1);
SDValue ResultVals[3];
unsigned NumResults = 0;
// If the call has results, copy the values out of the ret val registers.
- switch (Op.Val->getValueType(0).getSimpleVT()) {
+ switch (Op.getNode()->getValueType(0).getSimpleVT()) {
default: assert(0 && "Unexpected ret value!");
case MVT::Other: break;
case MVT::i32:
- if (Op.Val->getValueType(1) == MVT::i32) {
+ if (Op.getNode()->getValueType(1) == MVT::i32) {
Chain = DAG.getCopyFromReg(Chain, SPU::R4, MVT::i32, InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
Chain = DAG.getCopyFromReg(Chain, SPU::R3, MVT::i32,
@@ -1268,7 +1268,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
break;
case MVT::f32:
case MVT::f64:
- Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val->getValueType(0),
+ Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()->getValueType(0),
InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
NumResults = 1;
@@ -1278,7 +1278,7 @@ LowerCALL(SDValue Op, SelectionDAG &DAG, const SPUSubtarget *ST) {
case MVT::v4i32:
case MVT::v8i16:
case MVT::v16i8:
- Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.Val->getValueType(0),
+ Chain = DAG.getCopyFromReg(Chain, SPU::R3, Op.getNode()->getValueType(0),
InFlag).getValue(1);
ResultVals[0] = Chain.getValue(0);
NumResults = 1;
@@ -1301,7 +1301,7 @@ LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM) {
unsigned CC = DAG.getMachineFunction().getFunction()->getCallingConv();
bool isVarArg = DAG.getMachineFunction().getFunction()->isVarArg();
CCState CCInfo(CC, isVarArg, TM, RVLocs);
- CCInfo.AnalyzeReturn(Op.Val, RetCC_SPU);
+ CCInfo.AnalyzeReturn(Op.getNode(), RetCC_SPU);
// If this is the first return lowered for this function, add the regs to the
// liveout set for the function.
@@ -1321,7 +1321,7 @@ LowerRET(SDValue Op, SelectionDAG &DAG, TargetMachine &TM) {
Flag = Chain.getValue(1);
}
- if (Flag.Val)
+ if (Flag.getNode())
return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain, Flag);
else
return DAG.getNode(SPUISD::RET_FLAG, MVT::Other, Chain);
@@ -1339,13 +1339,13 @@ getVecImm(SDNode *N) {
// Check to see if this buildvec has a single non-undef value in its elements.
for (unsigned i = 0, e = N->getNumOperands(); i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
- if (OpVal.Val == 0)
+ if (OpVal.getNode() == 0)
OpVal = N->getOperand(i);
else if (OpVal != N->getOperand(i))
return 0;
}
- if (OpVal.Val != 0) {
+ if (OpVal.getNode() != 0) {
if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(OpVal)) {
return CN;
}
@@ -1599,7 +1599,7 @@ static SDValue LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
uint64_t UndefBits[2];
uint64_t SplatBits, SplatUndef;
int SplatSize;
- if (GetConstantBuildVectorBits(Op.Val, VectorBits, UndefBits)
+ if (GetConstantBuildVectorBits(Op.getNode(), VectorBits, UndefBits)
|| !isConstantSplat(VectorBits, UndefBits,
VT.getVectorElementType().getSizeInBits(),
SplatBits, SplatUndef, SplatSize))
@@ -1842,11 +1842,11 @@ static SDValue LowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG) {
static SDValue LowerSCALAR_TO_VECTOR(SDValue Op, SelectionDAG &DAG) {
SDValue Op0 = Op.getOperand(0); // Op0 = the scalar
- if (Op0.Val->getOpcode() == ISD::Constant) {
+ if (Op0.getNode()->getOpcode() == ISD::Constant) {
// For a constant, build the appropriate constant vector, which will
// eventually simplify to a vector register load.
- ConstantSDNode *CN = cast<ConstantSDNode>(Op0.Val);
+ ConstantSDNode *CN = cast<ConstantSDNode>(Op0.getNode());
SmallVector<SDValue, 16> ConstVecValues;
MVT VT;
size_t n_copies;
@@ -2447,25 +2447,25 @@ LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
ConstVec = Op.getOperand(0);
Arg = Op.getOperand(1);
- if (ConstVec.Val->getOpcode() != ISD::BUILD_VECTOR) {
- if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
+ if (ConstVec.getNode()->getOpcode() != ISD::BUILD_VECTOR) {
+ if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
ConstVec = ConstVec.getOperand(0);
} else {
ConstVec = Op.getOperand(1);
Arg = Op.getOperand(0);
- if (ConstVec.Val->getOpcode() == ISD::BIT_CONVERT) {
+ if (ConstVec.getNode()->getOpcode() == ISD::BIT_CONVERT) {
ConstVec = ConstVec.getOperand(0);
}
}
}
- if (ConstVec.Val->getOpcode() == ISD::BUILD_VECTOR) {
+ if (ConstVec.getNode()->getOpcode() == ISD::BUILD_VECTOR) {
uint64_t VectorBits[2];
uint64_t UndefBits[2];
uint64_t SplatBits, SplatUndef;
int SplatSize;
- if (!GetConstantBuildVectorBits(ConstVec.Val, VectorBits, UndefBits)
+ if (!GetConstantBuildVectorBits(ConstVec.getNode(), VectorBits, UndefBits)
&& isConstantSplat(VectorBits, UndefBits,
VT.getVectorElementType().getSizeInBits(),
SplatBits, SplatUndef, SplatSize)) {
@@ -2477,7 +2477,7 @@ LowerByteImmed(SDValue Op, SelectionDAG &DAG) {
for (size_t i = 0; i < tcVecSize; ++i)
tcVec[i] = tc;
- return DAG.getNode(Op.Val->getOpcode(), VT, Arg,
+ return DAG.getNode(Op.getNode()->getOpcode(), VT, Arg,
DAG.getNode(ISD::BUILD_VECTOR, VT, tcVec, tcVecSize));
}
}
@@ -2632,8 +2632,8 @@ SPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG)
default: {
cerr << "SPUTargetLowering::LowerOperation(): need to lower this!\n";
cerr << "Op.getOpcode() = " << Opc << "\n";
- cerr << "*Op.Val:\n";
- Op.Val->dump();
+ cerr << "*Op.getNode():\n";
+ Op.getNode()->dump();
abort();
}
case ISD::LOAD:
@@ -2796,7 +2796,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
DEBUG(cerr << "Replace: ");
DEBUG(N->dump(&DAG));
DEBUG(cerr << "\nWith: ");
- DEBUG(Op0.Val->dump(&DAG));
+ DEBUG(Op0.getNode()->dump(&DAG));
DEBUG(cerr << "\n");
return Op0;
@@ -2813,7 +2813,7 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
DEBUG(cerr << "Replace: ");
DEBUG(N->dump(&DAG));
DEBUG(cerr << "\nWith: ");
- DEBUG(Op0.Val->dump(&DAG));
+ DEBUG(Op0.getNode()->dump(&DAG));
DEBUG(cerr << "\n");
return Op0;
@@ -2871,11 +2871,11 @@ SPUTargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const
}
// Otherwise, return unchanged.
#if 1
- if (Result.Val) {
+ if (Result.getNode()) {
DEBUG(cerr << "\nReplace.SPU: ");
DEBUG(N->dump(&DAG));
DEBUG(cerr << "\nWith: ");
- DEBUG(Result.Val->dump(&DAG));
+ DEBUG(Result.getNode()->dump(&DAG));
DEBUG(cerr << "\n");
}
#endif
diff --git a/lib/Target/CellSPU/SPUOperands.td b/lib/Target/CellSPU/SPUOperands.td
index 252f2f8458..afe815c3c4 100644
--- a/lib/Target/CellSPU/SPUOperands.td
+++ b/lib/Target/CellSPU/SPUOperands.td
@@ -24,13 +24,13 @@ def LO16_vec : SDNodeXForm<scalar_to_vector, [{
&& "LO16_vec got something other than a BUILD_VECTOR");
// Get first constant operand...
- for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
+ for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() == 0 && i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
- if (OpVal.Val == 0)
+ if (OpVal.getNode() == 0)
OpVal = N->getOperand(i);
}
- assert(OpVal.Val != 0 && "LO16_vec did not locate a <defined> node");
+ assert(OpVal.getNode() != 0 && "LO16_vec did not locate a <defined> node");
ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
return getI32Imm((unsigned)CN->getValue() & 0xffff);
}]>;
@@ -49,13 +49,13 @@ def HI16_vec : SDNodeXForm<scalar_to_vector, [{
&& "HI16_vec got something other than a BUILD_VECTOR");
// Get first constant operand...
- for (unsigned i = 0, e = N->getNumOperands(); OpVal.Val == 0 && i != e; ++i) {
+ for (unsigned i = 0, e = N->getNumOperands(); OpVal.getNode() == 0 && i != e; ++i) {
if (N->getOperand(i).getOpcode() == ISD::UNDEF) continue;
- if (OpVal.Val == 0)
+ if (OpVal.getNode() == 0)
OpVal = N->getOperand(i);
}
- assert(OpVal.Val != 0 && "HI16_vec did not locate a <defined> node");
+ assert(OpVal.getNode() != 0 && "HI16_vec did not locate a <defined> node");
ConstantSDNode *CN = cast<ConstantSDNode>(OpVal);
return getI32Imm((unsigned)CN->getValue() >> 16);
}]>;
@@ -244,7 +244,7 @@ def v16i8SExt8Imm_xform: SDNodeXForm<build_vector, [{
// incoming constant being a 16-bit quantity, where the upper and lower bytes
// are EXACTLY the same (e.g., 0x2a2a)
def v16i8SExt8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
}], v16i8SExt8Imm_xform>;
// v16i8U8Imm_xform function: convert build_vector to unsigned 8-bit
@@ -259,7 +259,7 @@ def v16i8U8Imm_xform: SDNodeXForm<build_vector, [{
// incoming constant being a 16-bit quantity, where the upper and lower bytes
// are EXACTLY the same (e.g., 0x2a2a)
def v16i8U8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).Val != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i8).getNode() != 0;
}], v16i8U8Imm_xform>;
// v8i16SExt8Imm_xform function: convert build_vector to 8-bit sign extended
@@ -271,7 +271,7 @@ def v8i16SExt8Imm_xform: SDNodeXForm<build_vector, [{
// v8i16SExt8Imm: Predicate test for 8-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt8Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).Val != 0;
+ return SPU::get_vec_i8imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16SExt8Imm_xform>;
// v8i16SExt10Imm_xform function: convert build_vector to 16-bit sign extended
@@ -283,7 +283,7 @@ def v8i16SExt10Imm_xform: SDNodeXForm<build_vector, [{
// v8i16SExt10Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16SExt10Imm_xform>;
// v8i16Uns10Imm_xform function: convert build_vector to 16-bit unsigned
@@ -295,7 +295,7 @@ def v8i16Uns10Imm_xform: SDNodeXForm<build_vector, [{
// v8i16Uns10Imm: Predicate test for 16-bit unsigned immediate constant
// load, works in conjunction with its transform function.
def v8i16Uns10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).Val != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16Uns10Imm_xform>;
// v8i16SExt16Imm_xform function: convert build_vector to 16-bit sign extended
@@ -307,7 +307,7 @@ def v8i16Uns16Imm_xform: SDNodeXForm<build_vector, [{
// v8i16SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v8i16SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).Val != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i16).getNode() != 0;
}], v8i16Uns16Imm_xform>;
// v4i32SExt10Imm_xform function: convert build_vector to 10-bit sign extended
@@ -319,7 +319,7 @@ def v4i32SExt10Imm_xform: SDNodeXForm<build_vector, [{
// v4i32SExt10Imm: Predicate test for 10-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v4i32SExt10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32SExt10Imm_xform>;
// v4i32Uns10Imm_xform function: convert build_vector to 10-bit unsigned
@@ -331,7 +331,7 @@ def v4i32Uns10Imm_xform: SDNodeXForm<build_vector, [{
// v4i32Uns10Imm: Predicate test for 10-bit unsigned immediate constant
// load, works in conjunction with its transform function.
def v4i32Uns10Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).Val != 0;
+ return SPU::get_vec_i10imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32Uns10Imm_xform>;
// v4i32SExt16Imm_xform function: convert build_vector to 16-bit sign extended
@@ -343,7 +343,7 @@ def v4i32SExt16Imm_xform: SDNodeXForm<build_vector, [{
// v4i32SExt16Imm: Predicate test for 16-bit sign extended immediate constant
// load, works in conjunction with its transform function.
def v4i32SExt16Imm: PatLeaf<(build_vector), [{
- return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).Val != 0;
+ return SPU::get_vec_i16imm(N, *CurDAG, MVT::i32).getNode() != 0;
}], v4i32SExt16Imm_xform>;
// v4i32Uns18Imm_xform function: con