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-rw-r--r--lib/Target/ARM/ARMRegisterInfo.cpp15
-rw-r--r--lib/Target/ARM/ARMRegisterInfo.h2
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.cpp9
-rw-r--r--lib/Target/Alpha/AlphaRegisterInfo.h2
-rw-r--r--lib/Target/IA64/IA64RegisterInfo.cpp14
-rw-r--r--lib/Target/IA64/IA64RegisterInfo.h2
-rw-r--r--lib/Target/MRegisterInfo.cpp2
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.cpp39
-rw-r--r--lib/Target/PowerPC/PPCRegisterInfo.h2
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.cpp17
-rw-r--r--lib/Target/Sparc/SparcRegisterInfo.h2
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp16
-rw-r--r--lib/Target/X86/X86RegisterInfo.h6
13 files changed, 10 insertions, 118 deletions
diff --git a/lib/Target/ARM/ARMRegisterInfo.cpp b/lib/Target/ARM/ARMRegisterInfo.cpp
index 41f5e46104..a96be56384 100644
--- a/lib/Target/ARM/ARMRegisterInfo.cpp
+++ b/lib/Target/ARM/ARMRegisterInfo.cpp
@@ -28,7 +28,6 @@
#include "llvm/Target/TargetFrameInfo.h"
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
-#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/SmallVector.h"
#include "llvm/ADT/STLExtras.h"
#include <algorithm>
@@ -298,20 +297,6 @@ ARMRegisterInfo::getCalleeSavedRegClasses() const {
return CalleeSavedRegClasses;
}
-BitVector ARMRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(ARM::SP);
- if (STI.isTargetDarwin() || hasFP(MF))
- Reserved.set(FramePtr);
- // Some targets reserve R9.
- if (STI.isR9Reserved())
- Reserved.set(ARM::R9);
- // At PEI time, if LR is used, it will be spilled upon entry.
- if (MF.getUsedPhysregs() && !MF.isPhysRegUsed((unsigned)ARM::LR))
- Reserved.set(ARM::LR);
- return Reserved;
-}
-
/// hasFP - Return true if the specified function should have a dedicated frame
/// pointer register. This is true if the function has variable sized allocas
/// or if frame pointer elimination is disabled.
diff --git a/lib/Target/ARM/ARMRegisterInfo.h b/lib/Target/ARM/ARMRegisterInfo.h
index d5c8021e7a..e46da07b00 100644
--- a/lib/Target/ARM/ARMRegisterInfo.h
+++ b/lib/Target/ARM/ARMRegisterInfo.h
@@ -67,8 +67,6 @@ public:
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
- BitVector getReservedRegs(const MachineFunction &MF) const;
-
bool hasFP(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.cpp b/lib/Target/Alpha/AlphaRegisterInfo.cpp
index f08195e8be..bee76a2146 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.cpp
+++ b/lib/Target/Alpha/AlphaRegisterInfo.cpp
@@ -28,7 +28,6 @@
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
-#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
using namespace llvm;
@@ -179,14 +178,6 @@ AlphaRegisterInfo::getCalleeSavedRegClasses() const {
return CalleeSavedRegClasses;
}
-BitVector AlphaRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(Alpha::R15);
- Reserved.set(Alpha::R30);
- Reserved.set(Alpha::R31);
- return Reserved;
-}
-
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/Alpha/AlphaRegisterInfo.h b/lib/Target/Alpha/AlphaRegisterInfo.h
index 4629aaa9ae..5c3f8ecbf6 100644
--- a/lib/Target/Alpha/AlphaRegisterInfo.h
+++ b/lib/Target/Alpha/AlphaRegisterInfo.h
@@ -49,8 +49,6 @@ struct AlphaRegisterInfo : public AlphaGenRegisterInfo {
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
- BitVector getReservedRegs(const MachineFunction &MF) const;
-
bool hasFP(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
diff --git a/lib/Target/IA64/IA64RegisterInfo.cpp b/lib/Target/IA64/IA64RegisterInfo.cpp
index f5f8226686..cb9918fcb2 100644
--- a/lib/Target/IA64/IA64RegisterInfo.cpp
+++ b/lib/Target/IA64/IA64RegisterInfo.cpp
@@ -28,7 +28,6 @@
#include "llvm/Target/TargetOptions.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
@@ -107,19 +106,6 @@ IA64RegisterInfo::getCalleeSavedRegClasses() const {
return CalleeSavedRegClasses;
}
-BitVector IA64RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(IA64::r0);
- Reserved.set(IA64::r1);
- Reserved.set(IA64::r2);
- Reserved.set(IA64::r5);
- Reserved.set(IA64::r12);
- Reserved.set(IA64::r13);
- Reserved.set(IA64::r22);
- Reserved.set(IA64::rp);
- return Reserved;
-}
-
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/IA64/IA64RegisterInfo.h b/lib/Target/IA64/IA64RegisterInfo.h
index 9a97712230..42a2567bfa 100644
--- a/lib/Target/IA64/IA64RegisterInfo.h
+++ b/lib/Target/IA64/IA64RegisterInfo.h
@@ -48,8 +48,6 @@ struct IA64RegisterInfo : public IA64GenRegisterInfo {
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
- BitVector getReservedRegs(const MachineFunction &MF) const;
-
bool hasFP(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
diff --git a/lib/Target/MRegisterInfo.cpp b/lib/Target/MRegisterInfo.cpp
index 08039208fe..7caaae9d4f 100644
--- a/lib/Target/MRegisterInfo.cpp
+++ b/lib/Target/MRegisterInfo.cpp
@@ -41,7 +41,7 @@ BitVector MRegisterInfo::getAllocatableSet(MachineFunction &MF) const {
const TargetRegisterClass *RC = *I;
for (TargetRegisterClass::iterator I = RC->allocation_order_begin(MF),
E = RC->allocation_order_end(MF); I != E; ++I)
- Allocatable.set(*I);
+ Allocatable[*I] = true;
}
return Allocatable;
}
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp
index 7553634066..3370c362f9 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.cpp
+++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp
@@ -34,7 +34,6 @@
#include "llvm/Support/CommandLine.h"
#include "llvm/Support/Debug.h"
#include "llvm/Support/MathExtras.h"
-#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
#include <cstdlib>
using namespace llvm;
@@ -339,35 +338,6 @@ PPCRegisterInfo::getCalleeSavedRegClasses() const {
Darwin32_CalleeSavedRegClasses;
}
-// needsFP - Return true if the specified function should have a dedicated frame
-// pointer register. This is true if the function has variable sized allocas or
-// if frame pointer elimination is disabled.
-//
-static bool needsFP(const MachineFunction &MF) {
- const MachineFrameInfo *MFI = MF.getFrameInfo();
- return NoFramePointerElim || MFI->hasVarSizedObjects();
-}
-
-BitVector PPCRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(PPC::R0);
- Reserved.set(PPC::R1);
- Reserved.set(PPC::LR);
- // In Linux, r2 is reserved for the OS.
- if (!Subtarget.isDarwin())
- Reserved.set(PPC::R2);
- // On PPC64, r13 is the thread pointer. Never allocate this register.
- // Note that this is overconservative, as it also prevents allocation of
- // R31 when the FP is not needed.
- if (Subtarget.isPPC64()) {
- Reserved.set(PPC::R13);
- Reserved.set(PPC::R31);
- }
- if (needsFP(MF))
- Reserved.set(PPC::R31);
- return Reserved;
-}
-
/// foldMemoryOperand - PowerPC (like most RISC's) can only fold spills into
/// copy instructions, turning them into load/store instructions.
MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
@@ -428,6 +398,15 @@ MachineInstr *PPCRegisterInfo::foldMemoryOperand(MachineInstr *MI,
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
+// needsFP - Return true if the specified function should have a dedicated frame
+// pointer register. This is true if the function has variable sized allocas or
+// if frame pointer elimination is disabled.
+//
+static bool needsFP(const MachineFunction &MF) {
+ const MachineFrameInfo *MFI = MF.getFrameInfo();
+ return NoFramePointerElim || MFI->hasVarSizedObjects();
+}
+
// hasFP - Return true if the specified function actually has a dedicated frame
// pointer register. This is true if the function needs a frame pointer and has
// a non-zero stack size.
diff --git a/lib/Target/PowerPC/PPCRegisterInfo.h b/lib/Target/PowerPC/PPCRegisterInfo.h
index 6c30f6b2a5..f8344de6ac 100644
--- a/lib/Target/PowerPC/PPCRegisterInfo.h
+++ b/lib/Target/PowerPC/PPCRegisterInfo.h
@@ -58,8 +58,6 @@ public:
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
- BitVector getReservedRegs(const MachineFunction &MF) const;
-
/// targetHandlesStackFrameRounding - Returns true if the target is
/// responsible for rounding up the stack frame (probably at emitPrologue
/// time).
diff --git a/lib/Target/Sparc/SparcRegisterInfo.cpp b/lib/Target/Sparc/SparcRegisterInfo.cpp
index dab0b1037d..3cb5e502f9 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.cpp
+++ b/lib/Target/Sparc/SparcRegisterInfo.cpp
@@ -20,7 +20,6 @@
#include "llvm/CodeGen/MachineLocation.h"
#include "llvm/Target/TargetInstrInfo.h"
#include "llvm/Type.h"
-#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
@@ -117,22 +116,6 @@ const unsigned* SparcRegisterInfo::getCalleeSavedRegs() const {
return CalleeSavedRegs;
}
-BitVector SparcRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(SP::G2);
- Reserved.set(SP::G3);
- Reserved.set(SP::G4);
- Reserved.set(SP::O6);
- Reserved.set(SP::I6);
- Reserved.set(SP::I7);
- Reserved.set(SP::G0);
- Reserved.set(SP::G5);
- Reserved.set(SP::G6);
- Reserved.set(SP::G7);
- return Reserved;
-}
-
-
const TargetRegisterClass* const*
SparcRegisterInfo::getCalleeSavedRegClasses() const {
static const TargetRegisterClass * const CalleeSavedRegClasses[] = { 0 };
diff --git a/lib/Target/Sparc/SparcRegisterInfo.h b/lib/Target/Sparc/SparcRegisterInfo.h
index 763156a70c..6f80339c01 100644
--- a/lib/Target/Sparc/SparcRegisterInfo.h
+++ b/lib/Target/Sparc/SparcRegisterInfo.h
@@ -52,8 +52,6 @@ struct SparcRegisterInfo : public SparcGenRegisterInfo {
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
- BitVector getReservedRegs(const MachineFunction &MF) const;
-
bool hasFP(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
diff --git a/lib/Target/X86/X86RegisterInfo.cpp b/lib/Target/X86/X86RegisterInfo.cpp
index 65e847e0db..50fb091727 100644
--- a/lib/Target/X86/X86RegisterInfo.cpp
+++ b/lib/Target/X86/X86RegisterInfo.cpp
@@ -31,7 +31,6 @@
#include "llvm/Target/TargetMachine.h"
#include "llvm/Target/TargetOptions.h"
#include "llvm/Support/CommandLine.h"
-#include "llvm/ADT/BitVector.h"
#include "llvm/ADT/STLExtras.h"
using namespace llvm;
@@ -884,21 +883,6 @@ X86RegisterInfo::getCalleeSavedRegClasses() const {
return Is64Bit ? CalleeSavedRegClasses64Bit : CalleeSavedRegClasses32Bit;
}
-BitVector X86RegisterInfo::getReservedRegs(const MachineFunction &MF) const {
- BitVector Reserved(getNumRegs());
- Reserved.set(X86::RSP);
- Reserved.set(X86::ESP);
- Reserved.set(X86::SP);
- Reserved.set(X86::SPL);
- if (hasFP(MF)) {
- Reserved.set(X86::RBP);
- Reserved.set(X86::EBP);
- Reserved.set(X86::BP);
- Reserved.set(X86::BPL);
- }
- return Reserved;
-}
-
//===----------------------------------------------------------------------===//
// Stack Frame Processing methods
//===----------------------------------------------------------------------===//
diff --git a/lib/Target/X86/X86RegisterInfo.h b/lib/Target/X86/X86RegisterInfo.h
index d504675b05..0066fb6e1e 100644
--- a/lib/Target/X86/X86RegisterInfo.h
+++ b/lib/Target/X86/X86RegisterInfo.h
@@ -78,12 +78,6 @@ public:
/// length of this list match the getCalleeSavedRegs() list.
const TargetRegisterClass* const* getCalleeSavedRegClasses() const;
- /// getReservedRegs - Returns a bitset indexed by physical register number
- /// indicating if a register is a special register that has particular uses and
- /// should be considered unavailable at all times, e.g. SP, RA. This is used by
- /// register scavenger to determine what registers are free.
- BitVector getReservedRegs(const MachineFunction &MF) const;
-
bool hasFP(const MachineFunction &MF) const;
void eliminateCallFramePseudoInstr(MachineFunction &MF,
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-06-24 20:08:37 +0000