3 files changed, 20 insertions, 17 deletions
diff --git a/lib/Target/X86/X86.td b/lib/Target/X86/X86.td
index 0aafd60548..6c1a816c9f 100644
--- a/lib/Target/X86/X86.td
+++ b/lib/Target/X86/X86.td
@@ -131,10 +131,10 @@ def ProcIntelAtom : SubtargetFeature<"atom", "X86ProcFamily", "IntelAtom",
                     "Intel Atom processors">;
 
 class Proc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, GenericItineraries, Features>;
+ : ProcessorModel<Name, GenericModel, Features>;
 
 class AtomProc<string Name, list<SubtargetFeature> Features>
- : Processor<Name, AtomItineraries, Features>;
+ : ProcessorModel<Name, AtomModel, Features>;
 
 def : Proc<"generic",         []>;
 def : Proc<"i386",            []>;
diff --git a/lib/Target/X86/X86Schedule.td b/lib/Target/X86/X86Schedule.td
index 4331cf31e8..c14407f9ac 100644
--- a/lib/Target/X86/X86Schedule.td
+++ b/lib/Target/X86/X86Schedule.td
@@ -470,14 +470,12 @@ def IIC_NOP : InstrItinClass;
 // latencies. Since these latencies are not used for pipeline hazards,
 // they do not need to be exact.
 //
-// This set of instruction itineraries should contain no reference to
-// InstrStages. When an iterary has no stages, the scheduler can
-// bypass the logic needed for checking pipeline stage hazards.
-def GenericItineraries : MultiIssueItineraries<
-  4, // IssueWidth
-  0, // MinLatency
-  4, // LoadLatency (expected, may be overriden by OperandCycles)
- 10, // HighLatency (expected, may be overriden by OperandCycles)
- [], [], []>; // no FuncUnits, Bypasses, or InstrItinData.
+// The GenericModel contains no instruciton itineraries.
+def GenericModel : SchedMachineModel {
+  let IssueWidth = 4;
+  let MinLatency = 0;
+  let LoadLatency = 4;
+  let HighLatency = 10;
+}
 
 include "X86ScheduleAtom.td"
diff --git a/lib/Target/X86/X86ScheduleAtom.td b/lib/Target/X86/X86ScheduleAtom.td
index 56dd3407b2..87102614cc 100644
--- a/lib/Target/X86/X86ScheduleAtom.td
+++ b/lib/Target/X86/X86ScheduleAtom.td
@@ -22,12 +22,7 @@ def Port0 : FuncUnit; // ALU: ALU0, shift/rotate, load/store
 def Port1 : FuncUnit; // ALU: ALU1, bit processing, jump, and LEA
                       // SIMD/FP: SIMD ALU, FP Adder
 
-def AtomItineraries : MultiIssueItineraries<
-  2, // IssueWidth=2 allows 2 instructions per scheduling group.
-  1, // MinLatency=1. InstrStage cycles overrides MinLatency.
-     //               OperandCycles may be used for expected latency.
-  3, // LoadLatency (expected, may be overriden by OperandCycles)
-  30,// HighLatency (expected, may be overriden by OperandCycles)
+def AtomItineraries : ProcessorItineraries<
   [ Port0, Port1 ],
   [], [
   // P0 only
@@ -523,3 +518,13 @@ def AtomItineraries : MultiIssueItineraries<
   InstrItinData<IIC_NOP, [InstrStage<1, [Port0, Port1]>] >
   ]>;
 
+// Atom machine model.
+def AtomModel : SchedMachineModel {
+  let IssueWidth = 2;  // Allows 2 instructions per scheduling group.
+  let MinLatency = 1;  // InstrStage cycles overrides MinLatency.
+                       // OperandCycles may be used for expected latency.
+  let LoadLatency = 3; // Expected cycles, may be overriden by OperandCycles.
+  let HighLatency = 30;// Expected, may be overriden by OperandCycles.
+
+  let Itineraries = AtomItineraries;
+}