aboutsummaryrefslogtreecommitdiff
path: root/lib/Target/X86/X86ISelLowering.cpp
diff options
context:
space:
mode:
Diffstat (limited to 'lib/Target/X86/X86ISelLowering.cpp')
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp113
1 files changed, 68 insertions, 45 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index c73d8982ff..d18c283c4f 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -2746,7 +2746,7 @@ static SDValue CommuteVectorShuffle(SDValue Op, SDValue &V1,
}
std::swap(V1, V2);
- Mask = DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], NumElems);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
}
@@ -2771,7 +2771,7 @@ SDValue CommuteVectorShuffleMask(SDValue Mask, SelectionDAG &DAG, DebugLoc dl) {
else
MaskVec.push_back(DAG.getConstant(Val - NumElems, EltVT));
}
- return DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], NumElems);
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &MaskVec[0], NumElems);
}
@@ -2922,13 +2922,13 @@ static SDValue getZeroVector(MVT VT, bool HasSSE2, SelectionDAG &DAG,
SDValue Vec;
if (VT.getSizeInBits() == 64) { // MMX
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- Vec = DAG.getBUILD_VECTOR(MVT::v2i32, dl, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
} else if (HasSSE2) { // SSE2
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- Vec = DAG.getBUILD_VECTOR(MVT::v4i32, dl, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
} else { // SSE1
SDValue Cst = DAG.getTargetConstantFP(+0.0, MVT::f32);
- Vec = DAG.getBUILD_VECTOR(MVT::v4f32, dl, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4f32, Cst, Cst, Cst, Cst);
}
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
@@ -2943,9 +2943,9 @@ static SDValue getOnesVector(MVT VT, SelectionDAG &DAG, DebugLoc dl) {
SDValue Cst = DAG.getTargetConstant(~0U, MVT::i32);
SDValue Vec;
if (VT.getSizeInBits() == 64) // MMX
- Vec = DAG.getBUILD_VECTOR(MVT::v2i32, dl, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
else // SSE
- Vec = DAG.getBUILD_VECTOR(MVT::v4i32, dl, Cst, Cst, Cst, Cst);
+ Vec = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
return DAG.getNode(ISD::BIT_CONVERT, dl, VT, Vec);
}
@@ -2971,8 +2971,9 @@ static SDValue NormalizeMask(SDValue Mask, SelectionDAG &DAG) {
}
if (Changed)
- Mask = DAG.getBUILD_VECTOR(Mask.getValueType(), Mask.getDebugLoc(),
- &MaskVec[0], MaskVec.size());
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, Mask.getDebugLoc(),
+ Mask.getValueType(),
+ &MaskVec[0], MaskVec.size());
return Mask;
}
@@ -2986,7 +2987,8 @@ static SDValue getMOVLMask(unsigned NumElems, SelectionDAG &DAG, DebugLoc dl) {
MaskVec.push_back(DAG.getConstant(NumElems, BaseVT));
for (unsigned i = 1; i != NumElems; ++i)
MaskVec.push_back(DAG.getConstant(i, BaseVT));
- return DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], MaskVec.size());
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
}
/// getUnpacklMask - Returns a vector_shuffle mask for an unpackl operation
@@ -3000,7 +3002,8 @@ static SDValue getUnpacklMask(unsigned NumElems, SelectionDAG &DAG,
MaskVec.push_back(DAG.getConstant(i, BaseVT));
MaskVec.push_back(DAG.getConstant(i + NumElems, BaseVT));
}
- return DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], MaskVec.size());
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
}
/// getUnpackhMask - Returns a vector_shuffle mask for an unpackh operation
@@ -3015,7 +3018,8 @@ static SDValue getUnpackhMask(unsigned NumElems, SelectionDAG &DAG,
MaskVec.push_back(DAG.getConstant(i + Half, BaseVT));
MaskVec.push_back(DAG.getConstant(i + NumElems + Half, BaseVT));
}
- return DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], MaskVec.size());
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
}
/// getSwapEltZeroMask - Returns a vector_shuffle mask for a shuffle that swaps
@@ -3030,7 +3034,8 @@ static SDValue getSwapEltZeroMask(unsigned NumElems, unsigned DestElt,
MaskVec.push_back(DAG.getConstant(DestElt, BaseVT));
for (unsigned i = 1; i != NumElems; ++i)
MaskVec.push_back(DAG.getConstant(i == DestElt ? 0 : i, BaseVT));
- return DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], MaskVec.size());
+ return DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
}
/// PromoteSplat - Promote a splat of v4f32, v8i16 or v16i8 to v4i32.
@@ -3061,7 +3066,7 @@ static SDValue PromoteSplat(SDValue Op, SelectionDAG &DAG, bool HasSSE2) {
NumElems >>= 1;
}
SDValue Cst = DAG.getConstant(EltNo, MVT::i32);
- Mask = DAG.getBUILD_VECTOR(MVT::v4i32, dl, Cst, Cst, Cst, Cst);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32, Cst, Cst, Cst, Cst);
}
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
@@ -3097,12 +3102,13 @@ static SDValue CanonicalizeMovddup(SDValue Op, SDValue V1, SDValue Mask,
unsigned NumElems = PVT.getVectorNumElements();
if (NumElems == 2) {
SDValue Cst = DAG.getTargetConstant(0, MVT::i32);
- Mask = DAG.getBUILD_VECTOR(MVT::v2i32, dl, Cst, Cst);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32, Cst, Cst);
} else {
assert(NumElems == 4);
SDValue Cst0 = DAG.getTargetConstant(0, MVT::i32);
SDValue Cst1 = DAG.getTargetConstant(1, MVT::i32);
- Mask = DAG.getBUILD_VECTOR(MVT::v4i32, dl, Cst0, Cst1, Cst0, Cst1);
+ Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ Cst0, Cst1, Cst0, Cst1);
}
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, PVT, V1);
@@ -3131,7 +3137,8 @@ static SDValue getShuffleVectorZeroOrUndef(SDValue V2, unsigned Idx,
MaskVec.push_back(DAG.getConstant(NumElems, EVT));
else
MaskVec.push_back(DAG.getConstant(i, EVT));
- SDValue Mask = DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], MaskVec.size());
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2, Mask);
}
@@ -3417,7 +3424,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
SmallVector<SDValue, 8> MaskVec;
for (unsigned i = 0; i < NumElems; i++)
MaskVec.push_back(DAG.getConstant((i == Idx) ? 0 : 1, MaskEVT));
- SDValue Mask = DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], MaskVec.size());
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, Item,
DAG.getUNDEF(VT), Mask);
}
@@ -3506,8 +3514,8 @@ X86TargetLowering::LowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG) {
MaskVec.push_back(DAG.getConstant(1-i+NumElems, EVT));
else
MaskVec.push_back(DAG.getConstant(i+NumElems, EVT));
- SDValue ShufMask = DAG.getBUILD_VECTOR(MaskVT, dl,
- &MaskVec[0], MaskVec.size());
+ SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size());
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V[0], V[1], ShufMask);
}
@@ -3612,7 +3620,7 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
SmallVector<SDValue,8> MaskV;
MaskV.push_back(DAG.getConstant(BestLoQuad < 0 ? 0 : BestLoQuad, MVT::i64));
MaskV.push_back(DAG.getConstant(BestHiQuad < 0 ? 1 : BestHiQuad, MVT::i64));
- SDValue Mask = DAG.getBUILD_VECTOR(MVT::v2i64, dl, &MaskV[0], 2);
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i64, &MaskV[0], 2);
NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v2i64,
DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v2i64, V1),
@@ -3658,7 +3666,8 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
MVT::i16));
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
DAG.getUNDEF(MVT::v8i16),
- DAG.getBUILD_VECTOR(MVT::v8i16, dl, &MaskV[0], 8));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v8i16,
+ &MaskV[0], 8));
}
}
@@ -3685,7 +3694,8 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
}
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V1);
V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
- DAG.getBUILD_VECTOR(MVT::v16i8, dl, &pshufbMask[0], 16));
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MVT::v16i8, &pshufbMask[0], 16));
if (!TwoInputs)
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
@@ -3704,7 +3714,8 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
}
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v16i8, V2);
V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
- DAG.getBUILD_VECTOR(MVT::v16i8, dl, &pshufbMask[0], 16));
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MVT::v16i8, &pshufbMask[0], 16));
V1 = DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
return DAG.getNode(ISD::BIT_CONVERT, dl, MVT::v8i16, V1);
}
@@ -3730,7 +3741,8 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
MaskV.push_back(DAG.getConstant(i, MVT::i16));
NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
DAG.getUNDEF(MVT::v8i16),
- DAG.getBUILD_VECTOR(MVT::v8i16, dl, &MaskV[0], 8));
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MVT::v8i16, &MaskV[0], 8));
}
// If BestHi >= 0, generate a pshufhw to put the high elements in order,
@@ -3753,7 +3765,8 @@ SDValue LowerVECTOR_SHUFFLEv8i16(SDValue V1, SDValue V2,
}
NewV = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, MVT::v8i16, NewV,
DAG.getUNDEF(MVT::v8i16),
- DAG.getBUILD_VECTOR(MVT::v8i16, dl, &MaskV[0], 8));
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MVT::v8i16, &MaskV[0], 8));
}
// In case BestHi & BestLo were both -1, which means each quadword has a word
@@ -3839,7 +3852,8 @@ SDValue LowerVECTOR_SHUFFLEv16i8(SDValue V1, SDValue V2,
if (V2Only)
V1 = V2;
V1 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V1,
- DAG.getBUILD_VECTOR(MVT::v16i8, dl, &pshufbMask[0], 16));
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MVT::v16i8, &pshufbMask[0], 16));
if (!TwoInputs)
return V1;
@@ -3855,7 +3869,8 @@ SDValue LowerVECTOR_SHUFFLEv16i8(SDValue V1, SDValue V2,
pshufbMask.push_back(DAG.getConstant(EltIdx - 16, MVT::i8));
}
V2 = DAG.getNode(X86ISD::PSHUFB, dl, MVT::v16i8, V2,
- DAG.getBUILD_VECTOR(MVT::v16i8, dl, &pshufbMask[0], 16));
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MVT::v16i8, &pshufbMask[0], 16));
return DAG.getNode(ISD::OR, dl, MVT::v16i8, V1, V2);
}
@@ -3963,7 +3978,8 @@ SDValue RewriteAsNarrowerShuffle(SDValue V1, SDValue V2,
V1 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V1);
V2 = DAG.getNode(ISD::BIT_CONVERT, dl, NewVT, V2);
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, NewVT, V1, V2,
- DAG.getBUILD_VECTOR(MaskVT, dl, &MaskVec[0], MaskVec.size()));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskVec[0], MaskVec.size()));
}
/// getVZextMovL - Return a zero-extending vector move low node.
@@ -4040,7 +4056,8 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
// The second shuffle, which takes the first shuffle as both of its
// vector operands, put the elements into the right order.
V1 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
- DAG.getBUILD_VECTOR(MaskVT, dl, &Mask1[0], Mask1.size()));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &Mask1[0], Mask1.size()));
SmallVector<SDValue, 8> Mask2(4, DAG.getUNDEF(MaskEVT));
for (unsigned i = 0; i != 4; ++i) {
@@ -4054,8 +4071,8 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
}
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V1,
- DAG.getBUILD_VECTOR(MaskVT, dl,
- &Mask2[0], Mask2.size()));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &Mask2[0], Mask2.size()));
} else if (NumLo == 3 || NumHi == 3) {
// Otherwise, we must have three elements from one vector, call it X, and
// one element from the other, call it Y. First, use a shufps to build an
@@ -4086,7 +4103,7 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
Mask1[2] = PermMask.getOperand(HiIndex^1);
Mask1[3] = DAG.getUNDEF(MaskEVT);
V2 = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
- DAG.getBUILD_VECTOR(MaskVT, dl, &Mask1[0], 4));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT, &Mask1[0], 4));
if (HiIndex >= 2) {
Mask1[0] = PermMask.getOperand(0);
@@ -4094,7 +4111,8 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
Mask1[2] = DAG.getConstant(HiIndex & 1 ? 6 : 4, MaskEVT);
Mask1[3] = DAG.getConstant(HiIndex & 1 ? 4 : 6, MaskEVT);
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
- DAG.getBUILD_VECTOR(MaskVT, dl, &Mask1[0], 4));
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MaskVT, &Mask1[0], 4));
} else {
Mask1[0] = DAG.getConstant(HiIndex & 1 ? 2 : 0, MaskEVT);
Mask1[1] = DAG.getConstant(HiIndex & 1 ? 0 : 2, MaskEVT);
@@ -4109,7 +4127,8 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
DAG.getConstant(cast<ConstantSDNode>(Mask1[3])->getZExtValue()+4,
MaskEVT);
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V2, V1,
- DAG.getBUILD_VECTOR(MaskVT, dl, &Mask1[0], 4));
+ DAG.getNode(ISD::BUILD_VECTOR, dl,
+ MaskVT, &Mask1[0], 4));
}
}
@@ -4143,10 +4162,10 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
}
SDValue LoShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
- DAG.getBUILD_VECTOR(MaskVT, dl,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&LoMask[0], LoMask.size()));
SDValue HiShuffle = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, V1, V2,
- DAG.getBUILD_VECTOR(MaskVT, dl,
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
&HiMask[0], HiMask.size()));
SmallVector<SDValue, 8> MaskOps;
for (unsigned i = 0; i != 4; ++i) {
@@ -4158,7 +4177,8 @@ LowerVECTOR_SHUFFLE_4wide(SDValue V1, SDValue V2,
}
}
return DAG.getNode(ISD::VECTOR_SHUFFLE, dl, VT, LoShuffle, HiShuffle,
- DAG.getBUILD_VECTOR(MaskVT, dl, &MaskOps[0], MaskOps.size()));
+ DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &MaskOps[0], MaskOps.size()));
}
SDValue
@@ -4494,7 +4514,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
IdxVec.
push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
- SDValue Mask = DAG.getBUILD_VECTOR(MaskVT, dl, &IdxVec[0], IdxVec.size());
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &IdxVec[0], IdxVec.size());
SDValue Vec = Op.getOperand(0);
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
Vec, DAG.getUNDEF(Vec.getValueType()), Mask);
@@ -4516,7 +4537,8 @@ X86TargetLowering::LowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) {
IdxVec.push_back(DAG.getConstant(1, MaskVT.getVectorElementType()));
IdxVec.
push_back(DAG.getUNDEF(MaskVT.getVectorElementType()));
- SDValue Mask = DAG.getBUILD_VECTOR(MaskVT, dl, &IdxVec[0], IdxVec.size());
+ SDValue Mask = DAG.getNode(ISD::BUILD_VECTOR, dl, MaskVT,
+ &IdxVec[0], IdxVec.size());
SDValue Vec = Op.getOperand(0);
Vec = DAG.getNode(ISD::VECTOR_SHUFFLE, dl, Vec.getValueType(),
Vec, DAG.getUNDEF(Vec.getValueType()),
@@ -5017,13 +5039,13 @@ SDValue X86TargetLowering::LowerUINT_TO_FP_i64(SDValue Op, SelectionDAG &DAG) {
MaskVec.push_back(DAG.getConstant(4, MVT::i32));
MaskVec.push_back(DAG.getConstant(1, MVT::i32));
MaskVec.push_back(DAG.getConstant(5, MVT::i32));
- SDValue UnpcklMask = DAG.getBUILD_VECTOR(MVT::v4i32, dl,
- &MaskVec[0], MaskVec.size());
+ SDValue UnpcklMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v4i32,
+ &MaskVec[0], MaskVec.size());
SmallVector<SDValue, 4> MaskVec2;
MaskVec2.push_back(DAG.getConstant(1, MVT::i32));
MaskVec2.push_back(DAG.getConstant(0, MVT::i32));
- SDValue ShufMask = DAG.getBUILD_VECTOR(MVT::v2i32, dl,
- &MaskVec2[0], MaskVec2.size());
+ SDValue ShufMask = DAG.getNode(ISD::BUILD_VECTOR, dl, MVT::v2i32,
+ &MaskVec2[0], MaskVec2.size());
SDValue XR1 = DAG.getNode(ISD::SCALAR_TO_VECTOR, dl, MVT::v4i32,
DAG.getNode(ISD::EXTRACT_ELEMENT, dl, MVT::i32,
@@ -5488,7 +5510,8 @@ SDValue X86TargetLowering::LowerVSETCC(SDValue Op, SelectionDAG &DAG) {
SDValue SignBit = DAG.getConstant(APInt::getSignBit(EltVT.getSizeInBits()),
EltVT);
std::vector<SDValue> SignBits(VT.getVectorNumElements(), SignBit);
- SDValue SignVec = DAG.getBUILD_VECTOR(VT, dl, &SignBits[0], SignBits.size());
+ SDValue SignVec = DAG.getNode(ISD::BUILD_VECTOR, dl, VT, &SignBits[0],
+ SignBits.size());
Op0 = DAG.getNode(ISD::XOR, dl, VT, Op0, SignVec);
Op1 = DAG.getNode(ISD::XOR, dl, VT, Op1, SignVec);
}
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-15 20:52:29 +0000