1 files changed, 2 insertions, 19 deletions
diff --git a/lib/Target/X86/X86FastISel.cpp b/lib/Target/X86/X86FastISel.cpp
index 866d12fa59..96539b11fd 100644
--- a/lib/Target/X86/X86FastISel.cpp
+++ b/lib/Target/X86/X86FastISel.cpp
@@ -40,10 +40,6 @@ class X86FastISel : public FastISel {
   ///
   unsigned StackPtr;
 
-  /// GlobalBaseReg - keeps track of the virtual register mapped onto global
-  /// base register.
-  unsigned GlobalBaseReg;
-
   /// X86ScalarSSEf32, X86ScalarSSEf64 - Select between SSE or x87 
   /// floating point ops.
   /// When SSE is available, use it for f32 operations.
@@ -60,7 +56,6 @@ public:
     : FastISel(mf, mmi, vm, bm, am) {
     Subtarget = &TM.getSubtarget<X86Subtarget>();
     StackPtr = Subtarget->is64Bit() ? X86::RSP : X86::ESP;
-    GlobalBaseReg = 0;
     X86ScalarSSEf64 = Subtarget->hasSSE2();
     X86ScalarSSEf32 = Subtarget->hasSSE1();
   }
@@ -103,8 +98,6 @@ private:
 
   CCAssignFn *CCAssignFnForCall(unsigned CC, bool isTailCall = false);
 
-  unsigned getGlobalBaseReg();
-
   const X86InstrInfo *getInstrInfo() const {
     return getTargetMachine()->getInstrInfo();
   }
@@ -152,16 +145,6 @@ bool X86FastISel::isTypeLegal(const Type *Ty, const TargetLowering &TLI,
   return (AllowI1 && VT == MVT::i1) || TLI.isTypeLegal(VT);
 }
 
-/// getGlobalBaseReg - Return the the global base register. Output
-/// instructions required to initialize the global base register, if necessary.
-///
-unsigned X86FastISel::getGlobalBaseReg() {
-  assert(!Subtarget->is64Bit() && "X86-64 PIC uses RIP relative addressing");
-  if (!GlobalBaseReg)
-    GlobalBaseReg = getInstrInfo()->initializeGlobalBaseReg(MBB->getParent());
-  return GlobalBaseReg;
-}
-
 #include "X86GenCallingConv.inc"
 
 /// CCAssignFnForCall - Selects the correct CCAssignFn for a given calling
@@ -433,7 +416,7 @@ bool X86FastISel::X86SelectAddress(Value *V, X86AddressMode &AM, bool isCall) {
     if (!isCall &&
         TM.getRelocationModel() == Reloc::PIC_ &&
         !Subtarget->is64Bit())
-      AM.Base.Reg = getGlobalBaseReg();
+      AM.Base.Reg = getInstrInfo()->getGlobalBaseReg(&MF);
 
     // Emit an extra load if the ABI requires it.
     if (Subtarget->GVRequiresExtraLoad(GV, TM, isCall)) {
@@ -1042,7 +1025,7 @@ bool X86FastISel::X86SelectCall(Instruction *I) {
       TM.getRelocationModel() == Reloc::PIC_ &&
       Subtarget->isPICStyleGOT()) {
     TargetRegisterClass *RC = X86::GR32RegisterClass;
-    unsigned Base = getGlobalBaseReg();
+    unsigned Base = getInstrInfo()->getGlobalBaseReg(&MF);
     bool Emitted = TII.copyRegToReg(*MBB, MBB->end(), X86::EBX, Base, RC, RC);
     assert(Emitted && "Failed to emit a copy instruction!");
   }