diff options
Diffstat (limited to 'lib/Target/R600/SIInstrFormats.td')
| -rw-r--r-- | lib/Target/R600/SIInstrFormats.td | 36 |
1 files changed, 18 insertions, 18 deletions
diff --git a/lib/Target/R600/SIInstrFormats.td b/lib/Target/R600/SIInstrFormats.td index bd31bc1846..5c69c15920 100644 --- a/lib/Target/R600/SIInstrFormats.td +++ b/lib/Target/R600/SIInstrFormats.td @@ -22,25 +22,25 @@ //===----------------------------------------------------------------------===// class VOP3_32 <bits<9> op, string opName, list<dag> pattern> - : VOP3 <op, (outs VReg_32:$dst), (ins AllReg_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>; + : VOP3 <op, (outs VReg_32:$dst), (ins VSrc_32:$src0, VReg_32:$src1, VReg_32:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>; class VOP3_64 <bits<9> op, string opName, list<dag> pattern> - : VOP3 <op, (outs VReg_64:$dst), (ins AllReg_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>; + : VOP3 <op, (outs VReg_64:$dst), (ins VSrc_64:$src0, VReg_64:$src1, VReg_64:$src2, i32imm:$src3, i32imm:$src4, i32imm:$src5, i32imm:$src6), opName, pattern>; class SOP1_32 <bits<8> op, string opName, list<dag> pattern> - : SOP1 <op, (outs SReg_32:$dst), (ins SReg_32:$src0), opName, pattern>; + : SOP1 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0), opName, pattern>; class SOP1_64 <bits<8> op, string opName, list<dag> pattern> - : SOP1 <op, (outs SReg_64:$dst), (ins SReg_64:$src0), opName, pattern>; + : SOP1 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0), opName, pattern>; class SOP2_32 <bits<7> op, string opName, list<dag> pattern> - : SOP2 <op, (outs SReg_32:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>; + : SOP2 <op, (outs SReg_32:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>; class SOP2_64 <bits<7> op, string opName, list<dag> pattern> - : SOP2 <op, (outs SReg_64:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>; + : SOP2 <op, (outs SReg_64:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>; class SOP2_VCC <bits<7> op, string opName, list<dag> pattern> - : SOP2 <op, (outs SReg_1:$vcc), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>; + : SOP2 <op, (outs SReg_1:$vcc), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>; class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, string opName, list<dag> pattern> : @@ -49,7 +49,7 @@ class VOP1_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, >; multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> { - def _e32: VOP1_Helper <op, VReg_32, AllReg_32, opName, pattern>; + def _e32: VOP1_Helper <op, VReg_32, VSrc_32, opName, pattern>; def _e64 : VOP3_32 <{1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, opName, [] >; @@ -57,7 +57,7 @@ multiclass VOP1_32 <bits<8> op, string opName, list<dag> pattern> { multiclass VOP1_64 <bits<8> op, string opName, list<dag> pattern> { - def _e32 : VOP1_Helper <op, VReg_64, AllReg_64, opName, pattern>; + def _e32 : VOP1_Helper <op, VReg_64, VSrc_64, opName, pattern>; def _e64 : VOP3_64 < {1, 1, op{6}, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, @@ -73,7 +73,7 @@ class VOP2_Helper <bits<6> op, RegisterClass vrc, RegisterClass arc, multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> { - def _e32 : VOP2_Helper <op, VReg_32, AllReg_32, opName, pattern>; + def _e32 : VOP2_Helper <op, VReg_32, VSrc_32, opName, pattern>; def _e64 : VOP3_32 <{1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, opName, [] @@ -81,7 +81,7 @@ multiclass VOP2_32 <bits<6> op, string opName, list<dag> pattern> { } multiclass VOP2_64 <bits<6> op, string opName, list<dag> pattern> { - def _e32: VOP2_Helper <op, VReg_64, AllReg_64, opName, pattern>; + def _e32: VOP2_Helper <op, VReg_64, VSrc_64, opName, pattern>; def _e64 : VOP3_64 < {1, 0, 0, op{5}, op{4}, op{3}, op{2}, op{1}, op{0}}, @@ -112,16 +112,16 @@ multiclass VOPC_Helper <bits<8> op, RegisterClass vrc, RegisterClass arc, } multiclass VOPC_32 <bits<8> op, string opName, list<dag> pattern> - : VOPC_Helper <op, VReg_32, AllReg_32, opName, pattern>; + : VOPC_Helper <op, VReg_32, VSrc_32, opName, pattern>; multiclass VOPC_64 <bits<8> op, string opName, list<dag> pattern> - : VOPC_Helper <op, VReg_64, AllReg_64, opName, pattern>; + : VOPC_Helper <op, VReg_64, VSrc_64, opName, pattern>; class SOPC_32 <bits<7> op, string opName, list<dag> pattern> - : SOPC <op, (outs SCCReg:$dst), (ins SReg_32:$src0, SReg_32:$src1), opName, pattern>; + : SOPC <op, (outs SCCReg:$dst), (ins SSrc_32:$src0, SSrc_32:$src1), opName, pattern>; class SOPC_64 <bits<7> op, string opName, list<dag> pattern> - : SOPC <op, (outs SCCReg:$dst), (ins SReg_64:$src0, SReg_64:$src1), opName, pattern>; + : SOPC <op, (outs SCCReg:$dst), (ins SSrc_64:$src0, SSrc_64:$src1), opName, pattern>; class MIMG_Load_Helper <bits<7> op, string asm> : MIMG < op, @@ -140,7 +140,7 @@ class MTBUF_Store_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBU (outs), (ins regClass:$vdata, i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, - GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SReg_32:$soffset), + GPR4Align<SReg_128>:$srsrc, i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset), asm, []> { let mayStore = 1; @@ -152,7 +152,7 @@ class MUBUF_Load_Helper <bits<7> op, string asm, RegisterClass regClass> : MUBUF (outs regClass:$dst), (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, i1imm:$lds, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, i1imm:$slc, - i1imm:$tfe, SReg_32:$soffset), + i1imm:$tfe, SSrc_32:$soffset), asm, []> { let mayLoad = 1; @@ -164,7 +164,7 @@ class MTBUF_Load_Helper <bits<3> op, string asm, RegisterClass regClass> : MTBUF (outs regClass:$dst), (ins i16imm:$offset, i1imm:$offen, i1imm:$idxen, i1imm:$glc, i1imm:$addr64, i8imm:$dfmt, i8imm:$nfmt, VReg_32:$vaddr, GPR4Align<SReg_128>:$srsrc, - i1imm:$slc, i1imm:$tfe, SReg_32:$soffset), + i1imm:$slc, i1imm:$tfe, SSrc_32:$soffset), asm, []> { let mayLoad = 1; |