diff options
Diffstat (limited to 'lib/Target/IA64')
| -rw-r--r-- | lib/Target/IA64/IA64InstrInfo.cpp | 73 |
1 files changed, 43 insertions, 30 deletions
diff --git a/lib/Target/IA64/IA64InstrInfo.cpp b/lib/Target/IA64/IA64InstrInfo.cpp index a3009b2078..a6e4d97f6e 100644 --- a/lib/Target/IA64/IA64InstrInfo.cpp +++ b/lib/Target/IA64/IA64InstrInfo.cpp @@ -62,21 +62,24 @@ IA64InstrInfo::InsertBranch(MachineBasicBlock &MBB,MachineBasicBlock *TBB, } bool IA64InstrInfo::copyRegToReg(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, unsigned SrcReg, - const TargetRegisterClass *DestRC, - const TargetRegisterClass *SrcRC) const { + MachineBasicBlock::iterator MI, + unsigned DestReg, unsigned SrcReg, + const TargetRegisterClass *DestRC, + const TargetRegisterClass *SrcRC) const { if (DestRC != SrcRC) { // Not yet supported! return false; } + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); + if(DestRC == IA64::PRRegisterClass ) // if a bool, we use pseudocode // (SrcReg) DestReg = cmp.eq.unc(r0, r0) - BuildMI(MBB, MI, get(IA64::PCMPEQUNC), DestReg) + BuildMI(MBB, MI, DL, get(IA64::PCMPEQUNC), DestReg) .addReg(IA64::r0).addReg(IA64::r0).addReg(SrcReg); else // otherwise, MOV works (for both gen. regs and FP regs) - BuildMI(MBB, MI, get(IA64::MOV), DestReg).addReg(SrcReg); + BuildMI(MBB, MI, DL, get(IA64::MOV), DestReg).addReg(SrcReg); return true; } @@ -86,30 +89,34 @@ void IA64InstrInfo::storeRegToStackSlot(MachineBasicBlock &MBB, unsigned SrcReg, bool isKill, int FrameIdx, const TargetRegisterClass *RC) const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); if (RC == IA64::FPRegisterClass) { - BuildMI(MBB, MI, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) + BuildMI(MBB, MI, DL, get(IA64::STF_SPILL)).addFrameIndex(FrameIdx) .addReg(SrcReg, false, false, isKill); } else if (RC == IA64::GRRegisterClass) { - BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx) + BuildMI(MBB, MI, DL, get(IA64::ST8)).addFrameIndex(FrameIdx) .addReg(SrcReg, false, false, isKill); } else if (RC == IA64::PRRegisterClass) { /* we use IA64::r2 as a temporary register for doing this hackery. */ // first we load 0: - BuildMI(MBB, MI, get(IA64::MOV), IA64::r2).addReg(IA64::r0); + BuildMI(MBB, MI, DL, get(IA64::MOV), IA64::r2).addReg(IA64::r0); // then conditionally add 1: - BuildMI(MBB, MI, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) + BuildMI(MBB, MI, DL, get(IA64::CADDIMM22), IA64::r2).addReg(IA64::r2) .addImm(1).addReg(SrcReg, false, false, isKill); // and then store it to the stack - BuildMI(MBB, MI, get(IA64::ST8)).addFrameIndex(FrameIdx).addReg(IA64::r2); + BuildMI(MBB, MI, DL, get(IA64::ST8)) + .addFrameIndex(FrameIdx) + .addReg(IA64::r2); } else assert(0 && "sorry, I don't know how to store this sort of reg in the stack\n"); } void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, - bool isKill, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, + bool isKill, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { unsigned Opc = 0; if (RC == IA64::FPRegisterClass) { @@ -140,28 +147,34 @@ void IA64InstrInfo::storeRegToAddr(MachineFunction &MF, unsigned SrcReg, } void IA64InstrInfo::loadRegFromStackSlot(MachineBasicBlock &MBB, - MachineBasicBlock::iterator MI, - unsigned DestReg, int FrameIdx, - const TargetRegisterClass *RC)const{ + MachineBasicBlock::iterator MI, + unsigned DestReg, int FrameIdx, + const TargetRegisterClass *RC)const{ + DebugLoc DL = DebugLoc::getUnknownLoc(); + if (MI != MBB.end()) DL = MI->getDebugLoc(); if (RC == IA64::FPRegisterClass) { - BuildMI(MBB, MI, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); + BuildMI(MBB, MI, DL, get(IA64::LDF_FILL), DestReg).addFrameIndex(FrameIdx); } else if (RC == IA64::GRRegisterClass) { - BuildMI(MBB, MI, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); - } else if (RC == IA64::PRRegisterClass) { - // first we load a byte from the stack into r2, our 'predicate hackery' - // scratch reg - BuildMI(MBB, MI, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); - // then we compare it to zero. If it _is_ zero, compare-not-equal to - // r0 gives us 0, which is what we want, so that's nice. - BuildMI(MBB, MI, get(IA64::CMPNE), DestReg).addReg(IA64::r2).addReg(IA64::r0); - } else assert(0 && - "sorry, I don't know how to load this sort of reg from the stack\n"); + BuildMI(MBB, MI, DL, get(IA64::LD8), DestReg).addFrameIndex(FrameIdx); + } else if (RC == IA64::PRRegisterClass) { + // first we load a byte from the stack into r2, our 'predicate hackery' + // scratch reg + BuildMI(MBB, MI, DL, get(IA64::LD8), IA64::r2).addFrameIndex(FrameIdx); + // then we compare it to zero. If it _is_ zero, compare-not-equal to + // r0 gives us 0, which is what we want, so that's nice. + BuildMI(MBB, MI, DL, get(IA64::CMPNE), DestReg) + .addReg(IA64::r2) + .addReg(IA64::r0); + } else { + assert(0 && + "sorry, I don't know how to load this sort of reg from the stack\n"); + } } void IA64InstrInfo::loadRegFromAddr(MachineFunction &MF, unsigned DestReg, - SmallVectorImpl<MachineOperand> &Addr, - const TargetRegisterClass *RC, + SmallVectorImpl<MachineOperand> &Addr, + const TargetRegisterClass *RC, SmallVectorImpl<MachineInstr*> &NewMIs) const { unsigned Opc = 0; if (RC == IA64::FPRegisterClass) { |