1 files changed, 0 insertions, 24 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp
index 8a377d056a..1a20b2951d 100644
--- a/lib/Target/Alpha/AlphaISelPattern.cpp
+++ b/lib/Target/Alpha/AlphaISelPattern.cpp
@@ -116,8 +116,6 @@ public:
     CCInvMap.clear();
   }
 
-  virtual void EmitFunctionEntryCode(Function &Fn, MachineFunction &MF);
-
   unsigned SelectExpr(SDOperand N);
   void Select(SDOperand N);
 
@@ -135,28 +133,6 @@ public:
 };
 }
 
-void AlphaISel::EmitFunctionEntryCode(Function &Fn, MachineFunction &MF) {
-  // If this function has live-in values, emit the copies from pregs to vregs at
-  // the top of the function, before anything else.
-  MachineBasicBlock *BB = MF.begin();
-  if (MF.livein_begin() != MF.livein_end()) {
-    SSARegMap *RegMap = MF.getSSARegMap();
-    for (MachineFunction::livein_iterator LI = MF.livein_begin(),
-           E = MF.livein_end(); LI != E; ++LI) {
-      const TargetRegisterClass *RC = RegMap->getRegClass(LI->second);
-      if (RC == Alpha::GPRCRegisterClass) {
-        BuildMI(BB, Alpha::BIS, 2, LI->second).addReg(LI->first)
-          .addReg(LI->first);
-      } else if (RC == Alpha::FPRCRegisterClass) {
-        BuildMI(BB, Alpha::CPYS, 2, LI->second).addReg(LI->first)
-          .addReg(LI->first);
-      } else {
-        assert(0 && "Unknown regclass!");
-      }
-    }
-  }
-}
-
 static bool isSIntImmediate(SDOperand N, int64_t& Imm) {
   // test for constant
   if (ConstantSDNode *CN = dyn_cast<ConstantSDNode>(N)) {