diff options
Diffstat (limited to 'lib/Target/ARM/ARMMCCodeEmitter.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMMCCodeEmitter.cpp | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/lib/Target/ARM/ARMMCCodeEmitter.cpp b/lib/Target/ARM/ARMMCCodeEmitter.cpp index 5757046e99..b276301367 100644 --- a/lib/Target/ARM/ARMMCCodeEmitter.cpp +++ b/lib/Target/ARM/ARMMCCodeEmitter.cpp @@ -99,7 +99,7 @@ public: unsigned getBitfieldInvertedMaskOpValue(const MCInst &MI, unsigned Op) const; unsigned getRegisterListOpValue(const MCInst &MI, unsigned Op) const; - + unsigned getAddrMode6RegisterOperand(const MCInst &MI, unsigned Op) const; unsigned getNumFixupKinds() const { assert(0 && "ARMMCCodeEmitter::getNumFixupKinds() not yet implemented."); @@ -296,6 +296,22 @@ unsigned ARMMCCodeEmitter::getRegisterListOpValue(const MCInst &MI, return Binary; } +unsigned ARMMCCodeEmitter::getAddrMode6RegisterOperand(const MCInst &MI, + unsigned Op) const { + const MCOperand &Reg = MI.getOperand(Op); + const MCOperand &Imm = MI.getOperand(Op+1); + + unsigned RegNo = getARMRegisterNumbering(Reg.getReg()); + unsigned Align = Imm.getImm(); + switch(Align) { + case 8: Align = 0x01; break; + case 16: Align = 0x02; break; + case 32: Align = 0x03; break; + default: Align = 0x00; + } + return RegNo | (Align << 4); +} + void ARMMCCodeEmitter:: EncodeInstruction(const MCInst &MI, raw_ostream &OS, SmallVectorImpl<MCFixup> &Fixups) const { |