diff options
Diffstat (limited to 'lib/Target/ARM/ARMExpandPseudoInsts.cpp')
| -rw-r--r-- | lib/Target/ARM/ARMExpandPseudoInsts.cpp | 34 |
1 files changed, 32 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMExpandPseudoInsts.cpp b/lib/Target/ARM/ARMExpandPseudoInsts.cpp index 1c02c34e82..cdea8d36e0 100644 --- a/lib/Target/ARM/ARMExpandPseudoInsts.cpp +++ b/lib/Target/ARM/ARMExpandPseudoInsts.cpp @@ -699,6 +699,36 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { MI.eraseFromParent(); break; } + case ARM::t2LDRHpci: + case ARM::t2LDRBpci: + case ARM::t2LDRSHpci: + case ARM::t2LDRSBpci: + case ARM::t2LDRpci: { + unsigned NewLdOpc; + if (Opcode == ARM::t2LDRpci) + NewLdOpc = ARM::t2LDRi12; + else if (Opcode == ARM::t2LDRHpci) + NewLdOpc = ARM::t2LDRHi12; + else if (Opcode == ARM::t2LDRBpci) + NewLdOpc = ARM::t2LDRBi12; + else if (Opcode == ARM::t2LDRSHpci) + NewLdOpc = ARM::t2LDRSHi12; + else if (Opcode == ARM::t2LDRSBpci) + NewLdOpc = ARM::t2LDRSBi12; + else + llvm_unreachable("Not a known opcode?"); + + unsigned DstReg = MI.getOperand(0).getReg(); + bool DstIsDead = MI.getOperand(0).isDead(); + MachineInstrBuilder MIB = + BuildMI(MBB, MBBI, MI.getDebugLoc(), + TII->get(NewLdOpc), DstReg) + .addOperand(MI.getOperand(1)); + (*MIB).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); + TransferImpOps(MI, MIB, MIB); + MI.eraseFromParent(); + break; + } case ARM::tLDRpci_pic: case ARM::t2LDRpci_pic: { unsigned NewLdOpc = (Opcode == ARM::tLDRpci_pic) @@ -706,9 +736,9 @@ bool ARMExpandPseudo::ExpandMBB(MachineBasicBlock &MBB) { unsigned DstReg = MI.getOperand(0).getReg(); bool DstIsDead = MI.getOperand(0).isDead(); MachineInstrBuilder MIB1 = - AddDefaultPred(BuildMI(MBB, MBBI, MI.getDebugLoc(), + BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(NewLdOpc), DstReg) - .addOperand(MI.getOperand(1))); + .addOperand(MI.getOperand(1)); (*MIB1).setMemRefs(MI.memoperands_begin(), MI.memoperands_end()); MachineInstrBuilder MIB2 = BuildMI(MBB, MBBI, MI.getDebugLoc(), TII->get(ARM::tPICADD)) |