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-rw-r--r--lib/CodeGen/LowerSubregs.cpp10
-rw-r--r--lib/CodeGen/PHIElimination.cpp6
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAG.cpp10
-rw-r--r--lib/CodeGen/TwoAddressInstructionPass.cpp3
-rw-r--r--lib/CodeGen/VirtRegMap.cpp6
5 files changed, 18 insertions, 17 deletions
diff --git a/lib/CodeGen/LowerSubregs.cpp b/lib/CodeGen/LowerSubregs.cpp
index 668a9e5540..4172b12857 100644
--- a/lib/CodeGen/LowerSubregs.cpp
+++ b/lib/CodeGen/LowerSubregs.cpp
@@ -63,6 +63,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
assert(MI->getOperand(0).isRegister() && MI->getOperand(0).isDef() &&
MI->getOperand(1).isRegister() && MI->getOperand(1).isUse() &&
@@ -88,7 +89,7 @@ bool LowerSubregsInstructionPass::LowerExtract(MachineInstr *MI) {
assert(TRC == getPhysicalRegisterRegClass(MRI, SrcReg) &&
"Extract subreg and Dst must be of same register class");
- MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
+ TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC, TRC);
MachineBasicBlock::iterator dMI = MI;
DOUT << "subreg: " << *(--dMI);
}
@@ -103,6 +104,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
MachineBasicBlock *MBB = MI->getParent();
MachineFunction &MF = *MBB->getParent();
const MRegisterInfo &MRI = *MF.getTarget().getRegisterInfo();
+ const TargetInstrInfo &TII = *MF.getTarget().getInstrInfo();
unsigned DstReg = 0;
unsigned SrcReg = 0;
unsigned InsReg = 0;
@@ -157,7 +159,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
} else {
TRC1 = MF.getRegInfo().getRegClass(InsReg);
}
- MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+ TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
@@ -184,7 +186,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
assert(TRC0 == getPhysicalRegisterRegClass(MRI, SrcReg) &&
"Insert superreg and Dst must be of same register class");
- MRI.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
+ TII.copyRegToReg(*MBB, MI, DstReg, SrcReg, TRC0, TRC0);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
@@ -206,7 +208,7 @@ bool LowerSubregsInstructionPass::LowerInsert(MachineInstr *MI) {
} else {
TRC1 = MF.getRegInfo().getRegClass(InsReg);
}
- MRI.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
+ TII.copyRegToReg(*MBB, MI, DstSubReg, InsReg, TRC1, TRC1);
#ifndef NDEBUG
MachineBasicBlock::iterator dMI = MI;
diff --git a/lib/CodeGen/PHIElimination.cpp b/lib/CodeGen/PHIElimination.cpp
index 764e89b6da..07c4ef3f50 100644
--- a/lib/CodeGen/PHIElimination.cpp
+++ b/lib/CodeGen/PHIElimination.cpp
@@ -134,8 +134,8 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
// after any remaining phi nodes) which copies the new incoming register
// into the phi node destination.
//
- const MRegisterInfo *RegInfo = MF.getTarget().getRegisterInfo();
- RegInfo->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
+ const TargetInstrInfo *TII = MF.getTarget().getInstrInfo();
+ TII->copyRegToReg(MBB, AfterPHIsIt, DestReg, IncomingReg, RC, RC);
// Update live variable information if there is any...
LiveVariables *LV = getAnalysisToUpdate<LiveVariables>();
@@ -201,7 +201,7 @@ void PNE::LowerAtomicPHINode(MachineBasicBlock &MBB,
MachineBasicBlock::iterator I = opBlock.getFirstTerminator();
// Insert the copy.
- RegInfo->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC);
+ TII->copyRegToReg(opBlock, I, IncomingReg, SrcReg, RC, RC);
// Now update live variable information if we have it. Otherwise we're done
if (!LV) continue;
diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
index f506b3ebfb..1a5387bcf4 100644
--- a/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/ScheduleDAG.cpp
@@ -359,7 +359,7 @@ void ScheduleDAG::EmitCopyFromReg(SDNode *Node, unsigned ResNo,
} else {
// Create the reg, emit the copy.
VRBase = RegInfo.createVirtualRegister(TRC);
- MRI->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
+ TII->copyRegToReg(*BB, BB->end(), VRBase, SrcReg, TRC, TRC);
}
if (InstanceNo > 0)
@@ -751,7 +751,7 @@ void ScheduleDAG::EmitNode(SDNode *Node, unsigned InstanceNo,
TRC =
MRI->getPhysicalRegisterRegClass(Node->getOperand(2).getValueType(),
InReg);
- MRI->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
+ TII->copyRegToReg(*BB, BB->end(), DestReg, InReg, TRC, TRC);
}
break;
}
@@ -848,7 +848,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM
}
}
assert(I->Reg && "Unknown physical register!");
- MRI->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
+ TII->copyRegToReg(*BB, BB->end(), Reg, VRI->second,
SU->CopyDstRC, SU->CopySrcRC);
} else {
// Copy from physical register.
@@ -856,7 +856,7 @@ void ScheduleDAG::EmitCrossRCCopy(SUnit *SU, DenseMap<SUnit*, unsigned> &VRBaseM
unsigned VRBase = RegInfo.createVirtualRegister(SU->CopyDstRC);
bool isNew = VRBaseMap.insert(std::make_pair(SU, VRBase));
assert(isNew && "Node emitted out of order - early");
- MRI->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
+ TII->copyRegToReg(*BB, BB->end(), VRBase, I->Reg,
SU->CopyDstRC, SU->CopySrcRC);
}
break;
@@ -874,7 +874,7 @@ void ScheduleDAG::EmitSchedule() {
E = RegInfo.livein_end(); LI != E; ++LI)
if (LI->second) {
const TargetRegisterClass *RC = RegInfo.getRegClass(LI->second);
- MRI->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
+ TII->copyRegToReg(*MF.begin(), MF.begin()->end(), LI->second,
LI->first, RC, RC);
}
}
diff --git a/lib/CodeGen/TwoAddressInstructionPass.cpp b/lib/CodeGen/TwoAddressInstructionPass.cpp
index 4f92bdb6ca..dd71bec7eb 100644
--- a/lib/CodeGen/TwoAddressInstructionPass.cpp
+++ b/lib/CodeGen/TwoAddressInstructionPass.cpp
@@ -80,7 +80,6 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
DOUT << "Machine Function\n";
const TargetMachine &TM = MF.getTarget();
const TargetInstrInfo &TII = *TM.getInstrInfo();
- const MRegisterInfo &MRI = *TM.getRegisterInfo();
LiveVariables &LV = getAnalysis<LiveVariables>();
bool MadeChange = false;
@@ -193,7 +192,7 @@ bool TwoAddressInstructionPass::runOnMachineFunction(MachineFunction &MF) {
InstructionRearranged:
const TargetRegisterClass* rc = MF.getRegInfo().getRegClass(regA);
- MRI.copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
+ TII.copyRegToReg(*mbbi, mi, regA, regB, rc, rc);
MachineBasicBlock::iterator prevMi = prior(mi);
DOUT << "\t\tprepend:\t"; DEBUG(prevMi->print(*cerr.stream(), &TM));
diff --git a/lib/CodeGen/VirtRegMap.cpp b/lib/CodeGen/VirtRegMap.cpp
index 9100054169..dc215180c2 100644
--- a/lib/CodeGen/VirtRegMap.cpp
+++ b/lib/CodeGen/VirtRegMap.cpp
@@ -928,7 +928,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
DOUT << MBB.getBasicBlock()->getName() << ":\n";
MachineFunction &MF = *MBB.getParent();
-
+
// Spills - Keep track of which spilled values are available in physregs so
// that we can choose to reuse the physregs instead of emitting reloads.
AvailableSpills Spills(MRI, TII);
@@ -1182,7 +1182,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
const TargetRegisterClass* RC = RegInfo->getRegClass(VirtReg);
RegInfo->setPhysRegUsed(DesignatedReg);
ReusedOperands.markClobbered(DesignatedReg);
- MRI->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
+ TII->copyRegToReg(MBB, &MI, DesignatedReg, PhysReg, RC, RC);
MachineInstr *CopyMI = prior(MII);
UpdateKills(*CopyMI, RegKills, KillOps);
@@ -1268,7 +1268,7 @@ void LocalSpiller::RewriteMBB(MachineBasicBlock &MBB, VirtRegMap &VRM) {
DOUT << "Promoted Load To Copy: " << MI;
if (DestReg != InReg) {
const TargetRegisterClass *RC = RegInfo->getRegClass(VirtReg);
- MRI->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
+ TII->copyRegToReg(MBB, &MI, DestReg, InReg, RC, RC);
// Revisit the copy so we make sure to notice the effects of the
// operation on the destreg (either needing to RA it if it's
// virtual or needing to clobber any values if it's physical).
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-05-07 15:44:07 +0000