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-rw-r--r--lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp1881
1 files changed, 1115 insertions, 766 deletions
diff --git a/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp b/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp
index 83962537ce..088d089d80 100644
--- a/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp
+++ b/lib/CodeGen/TargetMachine/Sparc/SparcInstrSelection.cpp
@@ -7,8 +7,9 @@
//
// History:
// 7/02/01 - Vikram Adve - Created
-//***************************************************************************
+//**************************************************************************/
+#include "llvm/Support/MathExtras.h"
#include "llvm/Type.h"
#include "llvm/DerivedTypes.h"
#include "llvm/SymbolTable.h"
@@ -94,21 +95,17 @@ static unsigned FixConstantOperands(const InstructionNode* vmInstrNode,
unsigned numInstr,
TargetMachine& target);
-static unsigned InsertLoadConstInstructions(unsigned loadConstFlags,
- const InstructionNode* vmInstrNode,
- MachineInstr** mvec,
- unsigned numInstr);
-
-static MachineInstr* MakeOneLoadConstInstr(Instruction* vmInstr,
- Value* val,
- TmpInstruction*& tmpReg);
+static MachineInstr* MakeLoadConstInstr(Instruction* vmInstr,
+ Value* val,
+ TmpInstruction*& tmpReg,
+ MachineInstr*& getMinstr2);
static void ForwardOperand (InstructionNode* treeNode,
InstructionNode* parent,
int operandNum);
-//******************* Externally Visible Functions *************************/
+//************************ Internal Functions ******************************/
//------------------------------------------------------------------------
@@ -145,657 +142,8 @@ ThisIsAChainRule(int eruleno)
}
}
-//------------------------------------------------------------------------
-// External Function: GetInstructionsByRule
-//
-// Purpose:
-// Choose machine instructions for the SPARC according to the
-// patterns chosen by the BURG-generated parser.
-//------------------------------------------------------------------------
-
-unsigned
-GetInstructionsByRule(InstructionNode* subtreeRoot,
- int ruleForNode,
- short* nts,
- TargetMachine &target,
- MachineInstr** mvec)
-{
- int numInstr = 1; // initialize for common case
- bool checkCast = false; // initialize here to use fall-through
- Value *leftVal, *rightVal;
- const Type* opType;
- int nextRule;
- int forwardOperandNum = -1;
- BranchPattern brPattern;
- int64_t s0 = 0; // variables holding zero to avoid
- uint64_t u0 = 0; // overloading ambiguities below
-
- mvec[0] = mvec[1] = mvec[2] = mvec[3] = NULL; // just for safety
-
- switch(ruleForNode) {
- case 1: // stmt: Ret
- case 2: // stmt: RetValue(reg)
- // NOTE: Prepass of register allocation is responsible
- // for moving return value to appropriate register.
- // Mark the return-address register as a hidden virtual reg.
- {
- Instruction* returnReg = new TmpInstruction(Instruction::UserOp1,
- subtreeRoot->getInstruction(), NULL);
- subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(returnReg);
-
- mvec[0] = new MachineInstr(RETURN);
- mvec[0]->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,returnReg);
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed, s0);
-
- returnReg->addMachineInstruction(mvec[0]);
-
- mvec[numInstr++] = new MachineInstr(NOP); // delay slot
- break;
- }
-
- case 3: // stmt: Store(reg,reg)
- case 4: // stmt: Store(reg,ptrreg)
- mvec[0] = new MachineInstr(ChooseStoreInstruction(subtreeRoot->leftChild()->getValue()->getType()));
- SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 5: // stmt: BrUncond
- mvec[0] = new MachineInstr(BA);
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister, (Value*)NULL);
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
- ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
-
- mvec[numInstr++] = new MachineInstr(NOP); // delay slot
- break;
-
- case 6: // stmt: BrCond(boolconst)
- // boolconst => boolean was computed with `%b = setCC type reg1 constant'
- // If the constant is ZERO, we can use the branch-on-integer-register
- // instructions and avoid the SUBcc instruction entirely.
- // Otherwise this is just the same as case 5, so just fall through.
- {
- InstrTreeNode* constNode = subtreeRoot->leftChild()->rightChild();
- assert(constNode && constNode->getNodeType() ==InstrTreeNode::NTConstNode);
- ConstPoolVal* constVal = (ConstPoolVal*) constNode->getValue();
- bool isValidConst;
-
- if (constVal->getType()->isIntegral()
- && GetConstantValueAsSignedInt(constVal, isValidConst) == 0
- && isValidConst)
- {
- // That constant ia a zero after all...
- // Use the left child of the setCC instruction as the first argument!
- mvec[0] = new MachineInstr(ChooseBprInstruction(subtreeRoot));
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
- subtreeRoot->leftChild()->leftChild()->getValue());
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
- ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
- // delay slot
- mvec[numInstr++] = new MachineInstr(NOP);
-
- // false branch
- mvec[numInstr++] = new MachineInstr(BA);
- mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
- (Value*) NULL);
- mvec[numInstr-1]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp, ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
- break;
- }
- // ELSE FALL THROUGH
- }
-
- case 7: // stmt: BrCond(bool)
- // bool => boolean was computed with `%b = setcc type reg1 reg2'
- // Need to check whether the type was a FP, signed int or unsigned int,
- // and check the branching condition in order to choose the branch to use.
- //
- {
- bool isFPBranch;
- mvec[0] = new MachineInstr(ChooseBccInstruction(subtreeRoot, isFPBranch));
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
- subtreeRoot->leftChild()->getValue());
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
- ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
-
- // delay slot
- mvec[numInstr++] = new MachineInstr(NOP);
-
- // false branch
- mvec[numInstr++] = new MachineInstr(BA);
- mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
- (Value*) NULL);
- mvec[numInstr-1]->SetMachineOperand(0, MachineOperand::MO_PCRelativeDisp,
- ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(1));
- break;
- }
-
- case 8: // stmt: BrCond(boolreg)
- // bool => boolean is stored in an existing register.
- // Just use the branch-on-integer-register instruction!
- //
- mvec[0] = new MachineInstr(BRNZ);
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
- subtreeRoot->leftChild()->getValue());
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_PCRelativeDisp,
- ((BranchInst*) subtreeRoot->getInstruction())->getSuccessor(0));
- mvec[numInstr++] = new MachineInstr(NOP); // delay slot
- break;
-
- case 9: // stmt: Switch(reg)
- assert(0 && "*** SWITCH instruction is not implemented yet.");
- numInstr = 0;
- break;
-
- case 10: // reg: VRegList(reg, reg)
- assert(0 && "VRegList should never be the topmost non-chain rule");
- break;
-
- case 21: // reg: Not(reg): Implemented as reg = reg XOR-NOT 0
- mvec[0] = new MachineInstr(XNOR);
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
- subtreeRoot->leftChild()->getValue());
- mvec[0]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
- mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
- subtreeRoot->getValue());
- break;
-
- case 22: // reg: ToBoolTy(reg):
- opType = subtreeRoot->leftChild()->getValue()->getType();
- assert(opType->isIntegral() || opType == Type::BoolTy);
- numInstr = 0;
- forwardOperandNum = 0;
- break;
-
- case 23: // reg: ToUByteTy(reg)
- case 25: // reg: ToUShortTy(reg)
- case 27: // reg: ToUIntTy(reg)
- case 29: // reg: ToULongTy(reg)
- opType = subtreeRoot->leftChild()->getValue()->getType();
- assert(opType->isIntegral() ||
- opType->isPointerType() ||
- opType == Type::BoolTy && "Ignoring cast: illegal for other types");
- numInstr = 0;
- forwardOperandNum = 0;
- break;
-
- case 24: // reg: ToSByteTy(reg)
- case 26: // reg: ToShortTy(reg)
- case 28: // reg: ToIntTy(reg)
- case 30: // reg: ToLongTy(reg)
- opType = subtreeRoot->leftChild()->getValue()->getType();
- if (opType->isIntegral() || opType == Type::BoolTy)
- {
- numInstr = 0;
- forwardOperandNum = 0;
- }
- else
- {
- mvec[0] =new MachineInstr(ChooseConvertToIntInstr(subtreeRoot,opType));
- Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
- }
- break;
-
- case 31: // reg: ToFloatTy(reg):
- case 32: // reg: ToDoubleTy(reg):
-
- // If this instruction has a parent (a user) in the tree
- // and the user is translated as an FsMULd instruction,
- // then the cast is unnecessary. So check that first.
- // In the future, we'll want to do the same for the FdMULq instruction,
- // so do the check here instead of only for ToFloatTy(reg).
- //
- if (subtreeRoot->parent() != NULL &&
- ((InstructionNode*) subtreeRoot->parent())->getInstruction()->getMachineInstrVec()[0]->getOpCode() == FSMULD)
- {
- numInstr = 0;
- forwardOperandNum = 0;
- }
- else
- {
- opType = subtreeRoot->leftChild()->getValue()->getType();
- mvec[0] = new MachineInstr(ChooseConvertToFloatInstr(subtreeRoot, opType));
- Set2OperandsFromInstr(mvec[0], subtreeRoot, target);
- }
- break;
-
- case 19: // reg: ToArrayTy(reg):
- case 20: // reg: ToPointerTy(reg):
- numInstr = 0;
- forwardOperandNum = 0;
- break;
-
- case 33: // reg: Add(reg, reg)
- mvec[0] = new MachineInstr(ChooseAddInstruction(subtreeRoot));
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 34: // reg: Sub(reg, reg)
- mvec[0] = new MachineInstr(ChooseSubInstruction(subtreeRoot));
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 135: // reg: Mul(todouble, todouble)
- checkCast = true;
- // FALL THROUGH
-
- case 35: // reg: Mul(reg, reg)
- mvec[0] = new MachineInstr(ChooseMulInstruction(subtreeRoot, checkCast));
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 36: // reg: Div(reg, reg)
- mvec[0] = new MachineInstr(ChooseDivInstruction(subtreeRoot));
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 37: // reg: Rem(reg, reg)
- assert(0 && "REM instruction unimplemented for the SPARC.");
- break;
-
- case 38: // reg: And(reg, reg)
- mvec[0] = new MachineInstr(AND);
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 138: // reg: And(reg, not)
- mvec[0] = new MachineInstr(ANDN);
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 39: // reg: Or(reg, reg)
- mvec[0] = new MachineInstr(ORN);
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 139: // reg: Or(reg, not)
- mvec[0] = new MachineInstr(ORN);
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 40: // reg: Xor(reg, reg)
- mvec[0] = new MachineInstr(XOR);
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 140: // reg: Xor(reg, not)
- mvec[0] = new MachineInstr(XNOR);
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 41: // boolconst: SetCC(reg, Constant)
- // Check if this is an integer comparison, and
- // there is a parent, and the parent decided to use
- // a branch-on-integer-register instead of branch-on-condition-code.
- // If so, the SUBcc instruction is not required.
- // (However, we must still check for constants to be loaded from
- // the constant pool so that such a load can be associated with
- // this instruction.)
- //
- // Otherwise this is just the same as case 42, so just fall through.
- //
- if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral() &&
- subtreeRoot->parent() != NULL)
- {
- InstructionNode* parentNode = (InstructionNode*) subtreeRoot->parent();
- assert(parentNode->getNodeType() == InstrTreeNode::NTInstructionNode);
- const vector<MachineInstr*>&
- minstrVec = parentNode->getInstruction()->getMachineInstrVec();
- MachineOpCode parentOpCode;
- if (parentNode->getInstruction()->getOpcode() == Instruction::Br &&
- (parentOpCode = minstrVec[0]->getOpCode()) >= BRZ &&
- parentOpCode <= BRGEZ)
- {
- numInstr = 0; // don't forward the operand!
- break;
- }
- }
- // ELSE FALL THROUGH
-
- case 42: // bool: SetCC(reg, reg):
- {
- // If result of the SetCC is only used for a branch, we can
- // discard the result. otherwise, it must go into an integer register.
- // Note that the user may or may not be in the same tree, so we have
- // to follow SSA def-use edges here, not BURG tree edges.
- //
- Instruction* result = subtreeRoot->getInstruction();
- Value* firstUse = (Value*) * result->use_begin();
- bool discardResult =
- (result->use_size() == 1
- && firstUse->getValueType() == Value::InstructionVal
- && ((Instruction*) firstUse)->getOpcode() == Instruction::Br);
-
- bool mustClearReg;
- int valueToMove;
- MachineOpCode movOpCode;
-
- if (subtreeRoot->leftChild()->getValue()->getType()->isIntegral())
- {
- // integer condition: destination should be %g0 or integer register
- // if result must be saved but condition is not SetEQ then we need
- // a separate instruction to compute the bool result, so discard
- // result of SUBcc instruction anyway.
- //
- mvec[0] = new MachineInstr(SUBcc);
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target, discardResult);
-
- // mark the 4th operand as being a CC register, and a "result"
- mvec[0]->SetMachineOperand(3, MachineOperand::MO_CCRegister,
- subtreeRoot->getValue(), /*def*/ true);
-
- if (!discardResult)
- { // recompute bool if needed, using the integer condition codes
- if (result->getOpcode() == Instruction::SetNE)
- discardResult = true;
- else
- movOpCode =
- ChooseMovpccAfterSub(subtreeRoot, mustClearReg, valueToMove);
- }
- }
- else
- {
- // FP condition: dest of FCMP should be some FCCn register
- mvec[0] = new MachineInstr(ChooseFcmpInstruction(subtreeRoot));
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
- subtreeRoot->getValue());
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
- subtreeRoot->leftChild()->getValue());
- mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
- subtreeRoot->rightChild()->getValue());
-
- if (!discardResult)
- {// recompute bool using the FP condition codes
- mustClearReg = true;
- valueToMove = 1;
- movOpCode = ChooseMovFpccInstruction(subtreeRoot);
- }
- }
-
- if (!discardResult)
- {
- if (mustClearReg)
- {// Unconditionally set register to 0
- int n = numInstr++;
- mvec[n] = new MachineInstr(SETHI);
- mvec[n]->SetMachineOperand(0,MachineOperand::MO_UnextendedImmed,s0);
- mvec[n]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
- subtreeRoot->getValue());
- }
-
- // Now conditionally move `valueToMove' (0 or 1) into the register
- int n = numInstr++;
- mvec[n] = new MachineInstr(movOpCode);
- mvec[n]->SetMachineOperand(0, MachineOperand::MO_CCRegister,
- subtreeRoot->getValue());
- mvec[n]->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
- valueToMove);
- mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
- subtreeRoot->getValue());
- }
- break;
- }
-
- case 43: // boolreg: VReg
- case 44: // boolreg: Constant
- numInstr = 0;
- break;
-
- case 51: // reg: Load(reg)
- case 52: // reg: Load(ptrreg)
- case 53: // reg: LoadIdx(reg,reg)
- case 54: // reg: LoadIdx(ptrreg,reg)
- mvec[0] = new MachineInstr(ChooseLoadInstruction(subtreeRoot->getValue()->getType()));
- SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 55: // reg: GetElemPtr(reg)
- case 56: // reg: GetElemPtrIdx(reg,reg)
- if (subtreeRoot->parent() != NULL)
- {
- // Check if the parent was an array access.
- // If so, we still need to generate this instruction.
- MemAccessInst* memInst =(MemAccessInst*) subtreeRoot->getInstruction();
- const PointerType* ptrType =
- (const PointerType*) memInst->getPtrOperand()->getType();
- if (! ptrType->getValueType()->isArrayType())
- {// we don't need a separate instr
- numInstr = 0; // don't forward operand!
- break;
- }
- }
- // else in all other cases we need to a separate ADD instruction
- mvec[0] = new MachineInstr(ADD);
- SetOperandsForMemInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 57: // reg: Alloca: Implement as 2 instructions:
- // sub %sp, tmp -> %sp
- { // add %sp, 0 -> result
- Instruction* instr = subtreeRoot->getInstruction();
- const PointerType* instrType = (const PointerType*) instr->getType();
- assert(instrType->isPointerType());
- int tsize = (int) target.findOptimalStorageSize(instrType->getValueType());
- assert(tsize != 0 && "Just to check when this can happen");
- // if (tsize == 0)
- // {
- // numInstr = 0;
- // break;
- // }
- //else go on to create the instructions needed...
-
- // Create a temporary Value to hold the constant type-size
- ConstPoolSInt* valueForTSize = new ConstPoolSInt(Type::IntTy, tsize);
- ConstantPool &cpool = instr->getParent()->getParent()->getConstantPool();
- if (cpool.find(valueForTSize) == 0)
- cpool.insert(valueForTSize);
-
- // Instruction 1: sub %sp, tsize -> %sp
- // tsize is always constant, but it may have to be put into a
- // register if it doesn't fit in the immediate field.
- //
- mvec[0] = new MachineInstr(SUB);
- mvec[0]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, valueForTSize);
- mvec[0]->SetMachineOperand(2, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
-
- // Instruction 2: add %sp, 0 -> result
- numInstr++;
- mvec[1] = new MachineInstr(ADD);
- mvec[1]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
- mvec[1]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
- mvec[1]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, instr);
- break;
- }
-
- case 58: // reg: Alloca(reg): Implement as 3 instructions:
- // mul num, typeSz -> tmp
- // sub %sp, tmp -> %sp
- { // add %sp, 0 -> result
- Instruction* instr = subtreeRoot->getInstruction();
- const PointerType* instrType = (const PointerType*) instr->getType();
- assert(instrType->isPointerType() &&
- instrType->getValueType()->isArrayType());
- const Type* eltType =
- ((ArrayType*) instrType->getValueType())->getElementType();
- int tsize = (int) target.findOptimalStorageSize(eltType);
-
- assert(tsize != 0 && "Just to check when this can happen");
- // if (tsize == 0)
- // {
- // numInstr = 0;
- // break;
- // }
- //else go on to create the instructions needed...
-
- // Create a temporary Value to hold the constant type-size
- ConstPoolSInt* valueForTSize = new ConstPoolSInt(Type::IntTy, tsize);
- ConstantPool &cpool = instr->getParent()->getParent()->getConstantPool();
- if (cpool.find(valueForTSize) == 0)
- cpool.insert(valueForTSize);
-
- // Create a temporary value to hold `tmp'
- Instruction* tmpInstr = new TmpInstruction(Instruction::UserOp1,
- subtreeRoot->leftChild()->getValue(),
- NULL /*could insert tsize here*/);
- subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(tmpInstr);
-
- // Instruction 1: mul numElements, typeSize -> tmp
- mvec[0] = new MachineInstr(MULX);
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
- subtreeRoot->leftChild()->getValue());
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, valueForTSize);
- mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,tmpInstr);
-
- tmpInstr->addMachineInstruction(mvec[0]);
-
- // Instruction 2: sub %sp, tmp -> %sp
- numInstr++;
- mvec[1] = new MachineInstr(SUB);
- mvec[1]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
- mvec[1]->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,tmpInstr);
- mvec[1]->SetMachineOperand(2, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
-
- // Instruction 3: add %sp, 0 -> result
- numInstr++;
- mvec[2] = new MachineInstr(ADD);
- mvec[2]->SetMachineOperand(0, /*regNum %sp = o6 = r[14]*/(unsigned int)14);
- mvec[2]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
- mvec[2]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, instr);
- break;
- }
-
- case 61: // reg: Call
- // Generate a call-indirect (i.e., JMPL) for now to expose
- // the potential need for registers. If an absolute address
- // is available, replace this with a CALL instruction.
- // Mark both the indirection register and the return-address
- { // register as hidden virtual registers.
-
- Instruction* jmpAddrReg = new TmpInstruction(Instruction::UserOp1,
- ((CallInst*) subtreeRoot->getInstruction())->getCalledMethod(), NULL);
- Instruction* retAddrReg = new TmpInstruction(Instruction::UserOp1,
- subtreeRoot->getValue(), NULL);
- subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(jmpAddrReg);
- subtreeRoot->getInstruction()->getMachineInstrVec().addTempValue(retAddrReg);
-
- mvec[0] = new MachineInstr(JMPL);
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister, jmpAddrReg);
- mvec[0]->SetMachineOperand(1, MachineOperand::MO_SignExtendedImmed,
- (int64_t) 0);
- mvec[0]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, retAddrReg);
-
- // NOTE: jmpAddrReg will be loaded by a different instruction generated
- // by the final code generator, so we just mark the CALL instruction
- // as computing that value.
- // The retAddrReg is actually computed by the CALL instruction.
- //
- jmpAddrReg->addMachineInstruction(mvec[0]);
- retAddrReg->addMachineInstruction(mvec[0]);
-
- mvec[numInstr++] = new MachineInstr(NOP); // delay slot
- break;
- }
-
- case 62: // reg: Shl(reg, reg)
- opType = subtreeRoot->leftChild()->getValue()->getType();
- assert(opType->isIntegral() || opType == Type::BoolTy);
- mvec[0] = new MachineInstr((opType == Type::LongTy)? SLLX : SLL);
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 63: // reg: Shr(reg, reg)
- opType = subtreeRoot->leftChild()->getValue()->getType();
- assert(opType->isIntegral() || opType == Type::BoolTy);
- mvec[0] = new MachineInstr((opType->isSigned()
- ? ((opType == Type::LongTy)? SRAX : SRA)
- : ((opType == Type::LongTy)? SRLX : SRL)));
- Set3OperandsFromInstr(mvec[0], subtreeRoot, target);
- break;
-
- case 64: // reg: Phi(reg,reg)
- { // This instruction has variable #operands, so resultPos is 0.
- Instruction* phi = subtreeRoot->getInstruction();
- mvec[0] = new MachineInstr(PHI, 1 + phi->getNumOperands());
- mvec[0]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
- subtreeRoot->getValue(), true);
- for (unsigned i=0, N=phi->getNumOperands(); i < N; i++)
- mvec[0]->SetMachineOperand(i+1, MachineOperand::MO_VirtualRegister,
- phi->getOperand(i));
- break;
- }
- case 71: // reg: VReg
- case 72: // reg: Constant
- numInstr = 0; // don't forward the value
- break;
-
- case 111: // stmt: reg
- case 112: // stmt: boolconst
- case 113: // stmt: bool
- case 121:
- case 122:
- case 123:
- case 124:
- case 125:
- case 126:
- case 127:
- case 128:
- case 129:
- case 130:
- case 131:
- case 132:
- case 153:
- case 155:
- //
- // These are all chain rules, which have a single nonterminal on the RHS.
- // Get the rule that matches the RHS non-terminal and use that instead.
- //
- assert(ThisIsAChainRule(ruleForNode));
- assert(nts[0] && ! nts[1]
- && "A chain rule should have only one RHS non-terminal!");
- nextRule = burm_rule(subtreeRoot->getBasicNode()->state, nts[0]);
- nts = burm_nts[nextRule];
- numInstr = GetInstructionsByRule(subtreeRoot, nextRule, nts,target,mvec);
- break;
-
- default:
- assert(0 && "Unrecognized BURG rule");
- numInstr = 0;
- break;
- }
-
- if (forwardOperandNum >= 0)
- { // We did not generate a machine instruction but need to use operand.
- // If user is in the same tree, replace Value in its machine operand.
- // If not, insert a copy instruction which should get coalesced away
- // by register allocation.
- if (subtreeRoot->parent() != NULL)
- ForwardOperand(subtreeRoot, (InstructionNode*) subtreeRoot->parent(),
- forwardOperandNum);
- else
- {
- int n = numInstr++;
- mvec[n] = new MachineInstr(ADD);
- mvec[n]->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
- subtreeRoot->getInstruction()->getOperand(forwardOperandNum));
- mvec[n]->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
- mvec[n]->SetMachineOperand(2, MachineOperand::MO_VirtualRegister,
- subtreeRoot->getInstruction());
- }
- }
-
- if (! ThisIsAChainRule(ruleForNode))
- numInstr = FixConstantOperands(subtreeRoot, mvec, numInstr, target);
-
- return numInstr;
-}
-
-
-//---------------------------------------------------------------------------
-// Private helper routines for SPARC instruction selection.
-//---------------------------------------------------------------------------
-
-
-static MachineOpCode
+static inline MachineOpCode
ChooseBprInstruction(const InstructionNode* instrNode)
{
MachineOpCode opCode;
@@ -821,7 +169,7 @@ ChooseBprInstruction(const InstructionNode* instrNode)
}
-static MachineOpCode
+static inline MachineOpCode
ChooseBccInstruction(const InstructionNode* instrNode,
bool& isFPBranch)
{
@@ -838,7 +186,7 @@ ChooseBccInstruction(const InstructionNode* instrNode,
}
-static MachineOpCode
+static inline MachineOpCode
ChooseBpccInstruction(const InstructionNode* instrNode,
const BinaryOperator* setCCInstr)
{
@@ -880,7 +228,7 @@ ChooseBpccInstruction(const InstructionNode* instrNode,
return opCode;
}
-static MachineOpCode
+static inline MachineOpCode
ChooseBFpccInstruction(const InstructionNode* instrNode,
const BinaryOperator* setCCInstr)
{
@@ -903,7 +251,7 @@ ChooseBFpccInstruction(const InstructionNode* instrNode,
}
-static MachineOpCode
+static inline MachineOpCode
ChooseMovFpccInstruction(const InstructionNode* instrNode)
{
MachineOpCode opCode = INVALID_OPCODE;
@@ -962,7 +310,7 @@ ChooseMovpccAfterSub(const InstructionNode* instrNode,
}
-static MachineOpCode
+static inline MachineOpCode
ChooseConvertToFloatInstr(const InstructionNode* instrNode,
const Type* opType)
{
@@ -999,7 +347,7 @@ ChooseConvertToFloatInstr(const InstructionNode* instrNode,
return opCode;
}
-static MachineOpCode
+static inline MachineOpCode
ChooseConvertToIntInstr(const InstructionNode* instrNode,
const Type* opType)
{
@@ -1036,7 +384,7 @@ ChooseConvertToIntInstr(const InstructionNode* instrNode,
}
-static MachineOpCode
+static inline MachineOpCode
ChooseAddInstruction(const InstructionNode* instrNode)
{
MachineOpCode opCode = INVALID_OPCODE;
@@ -1064,7 +412,47 @@ ChooseAddInstruction(const InstructionNode* instrNode)
return opCode;
}
-static MachineOpCode
+
+static inline MachineInstr*
+CreateMovFloatInstruction(const InstructionNode* instrNode,
+ const Type* resultType)
+{
+ MachineInstr* minstr = new MachineInstr((resultType == Type::FloatTy)
+ ? FMOVS : FMOVD);
+ minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+ instrNode->leftChild()->getValue());
+ minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister,
+ instrNode->getValue());
+ return minstr;
+}
+
+static inline MachineInstr*
+CreateAddConstInstruction(const InstructionNode* instrNode)
+{
+ MachineInstr* minstr = NULL;
+
+ Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
+ assert(constOp->getValueType() == Value::ConstantVal);
+
+ // Cases worth optimizing are:
+ // (1) Add with 0 for float or double: use an FMOV of appropriate type,
+ // instead of an FADD (1 vs 3 cycles). There is no integer MOV.
+ //
+ const Type* resultType = instrNode->getInstruction()->getType();
+
+ if (resultType == Type::FloatTy ||
+ resultType == Type::DoubleTy)
+ {
+ double dval = ((ConstPoolFP*) constOp)->getValue();
+ if (dval == 0.0)
+ minstr = CreateMovFloatInstruction(instrNode, resultType);
+ }
+
+ return minstr;
+}
+
+
+static inline MachineOpCode
ChooseSubInstruction(const InstructionNode* instrNode)
{
MachineOpCode opCode = INVALID_OPCODE;
@@ -1091,7 +479,33 @@ ChooseSubInstruction(const InstructionNode* instrNode)
}
-static MachineOpCode
+static inline MachineInstr*
+CreateSubConstInstruction(const InstructionNode* instrNode)
+{
+ MachineInstr* minstr = NULL;
+
+ Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
+ assert(constOp->getValueType() == Value::ConstantVal);
+
+ // Cases worth optimizing are:
+ // (1) Sub with 0 for float or double: use an FMOV of appropriate type,
+ // instead of an FSUB (1 vs 3 cycles). There is no integer MOV.
+ //
+ const Type* resultType = instrNode->getInstruction()->getType();
+
+ if (resultType == Type::FloatTy ||
+ resultType == Type::DoubleTy)
+ {
+ double dval = ((ConstPoolFP*) constOp)->getValue();
+ if (dval == 0.0)
+ minstr = CreateMovFloatInstruction(instrNode, resultType);
+ }
+
+ return minstr;
+}
+
+
+static inline MachineOpCode
ChooseFcmpInstruction(const InstructionNode* instrNode)
{
MachineOpCode opCode = INVALID_OPCODE;
@@ -1101,38 +515,42 @@ ChooseFcmpInstruction(const InstructionNode* instrNode)
{
case Type::FloatTyID: opCode = FCMPS; break;
case Type::DoubleTyID: opCode = FCMPD; break;
- default: assert(0 && "Invalid type for ADD instruction"); break;
+ default: assert(0 && "Invalid type for FCMP instruction"); break;
}
return opCode;
}
-static MachineOpCode
+// Assumes that leftArg and rightArg are both cast instructions.
+//
+static inline bool
+BothFloatToDouble(const InstructionNode* instrNode)
+{
+ InstrTreeNode* leftArg = instrNode->leftChild();
+ InstrTreeNode* rightArg = instrNode->rightChild();
+ InstrTreeNode* leftArgArg = leftArg->leftChild();
+ InstrTreeNode* rightArgArg = rightArg->leftChild();
+ assert(leftArg->getValue()->getType() == rightArg->getValue()->getType());
+
+ // Check if both arguments are floats cast to double
+ return (leftArg->getValue()->getType() == Type::DoubleTy &&
+ leftArgArg->getValue()->getType() == Type::FloatTy &&
+ rightArgArg->getValue()->getType() == Type::FloatTy);
+}
+
+
+static inline MachineOpCode
ChooseMulInstruction(const InstructionNode* instrNode,
bool checkCasts)
{
MachineOpCode opCode = INVALID_OPCODE;
- if (checkCasts)
+ if (checkCasts && BothFloatToDouble(instrNode))
{
- // Assume that leftArg and rightArg are both cast instructions.
- //
- InstrTreeNode* leftArg = instrNode->leftChild();
- InstrTreeNode* rightArg = instrNode->rightChild();
- InstrTreeNode* leftArgArg = leftArg->leftChild();
- InstrTreeNode* rightArgArg = rightArg->leftChild();
- assert(leftArg->getValue()->getType() ==rightArg->getValue()->getType());
-
- // If both arguments are floats cast to double, use FsMULd
- if (leftArg->getValue()->getType() == Type::DoubleTy &&
- leftArgArg->getValue()->getType() == Type::FloatTy &&
- rightArgArg->getValue()->getType() == Type::FloatTy)
- {
- return opCode = FSMULD;
- }
- // else fall through and use the regular multiply instructions
+ return opCode = FSMULD;
}
+ // else fall through and use the regular multiply instructions
const Type* resultType = instrNode->getInstruction()->getType();
@@ -1154,7 +572,117 @@ ChooseMulInstruction(const InstructionNode* instrNode,
}
-static MachineOpCode
+static inline MachineInstr*
+CreateIntNegInstruction(Value* vreg)
+{
+ MachineInstr* minstr = new MachineInstr(SUB);
+ minstr->SetMachineOperand(0, /*regNum %g0*/(unsigned int) 0);
+ minstr->SetMachineOperand(1, MachineOperand::MO_VirtualRegister, vreg);
+ minstr->SetMachineOperand(2, MachineOperand::MO_VirtualRegister, vreg);
+ return minstr;
+}
+
+
+static inline MachineInstr*
+CreateMulConstInstruction(const InstructionNode* instrNode,
+ MachineInstr*& getMinstr2)
+{
+ MachineInstr* minstr = NULL;
+ getMinstr2 = NULL;
+ bool needNeg = false;
+
+ Value* constOp = ((InstrTreeNode*) instrNode->rightChild())->getValue();
+ assert(constOp->getValueType() == Value::ConstantVal);
+
+ // Cases worth optimizing are:
+ // (1) Multiply by 0 or 1 for any type: replace with copy (ADD or FMOV)
+ // (2) Multiply by 2^x for integer types: replace with Shift
+ //
+ const Type* resultType = instrNode->getInstruction()->getType();
+
+ if (resultType->isIntegral())
+ {
+ unsigned pow;
+ bool isValidConst;
+ int64_t C = GetConstantValueAsSignedInt(constOp, isValidConst);
+ if (isValidConst)
+ {
+ bool needNeg = false;
+ if (C < 0)
+ {
+ needNeg = true;
+ C = -C;
+ }
+
+ if (C == 0 || C == 1)
+ {
+ minstr = new MachineInstr(ADD);
+
+ if (C == 0)
+ minstr->SetMachineOperand(0, /*regNum %g0*/ (unsigned int) 0);
+ else
+ minstr->SetMachineOperand(0,MachineOperand::MO_VirtualRegister,
+ instrNode->leftChild()->getValue());
+ minstr->SetMachineOperand(1, /*regNum %g0*/ (unsigned int) 0);
+ }
+ else if (IsPowerOf2(C, pow))
+ {
+ minstr = new MachineInstr((resultType == Type::LongTy)
+ ? SLLX : SLL);
+ minstr->SetMachineOperand(0, MachineOperand::MO_VirtualRegister,
+ instrNode->leftChild()->getValue());
+ minstr->SetMachineOperand(1, MachineOperand::MO_UnextendedImmed,
+ pow);
+ }
+
+ if (minstr && needNeg)
+ { // insert <reg = SUB 0, reg> after the instr to flip the sign
+ getMinstr2 = CreateIntNegInstruction(instrNode->getValue());
+ }
+ }
+ }
+ else
+ {
+ if (resultType == Type::FloatTy ||
+ resultType == Type::DoubleTy)
+ {
+ bool isValidConst;
+ double dval = ((ConstPoolFP*) constOp)->getValue();