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-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp8
1 files changed, 5 insertions, 3 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
index 7702b3d5e9..3114d1b9bb 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp
@@ -133,16 +133,17 @@ namespace llvm {
/// for the target.
ScheduleDAG* createDefaultScheduler(SelectionDAGISel *IS,
SelectionDAG *DAG,
+ const TargetMachine *TM,
MachineBasicBlock *BB,
bool Fast) {
TargetLowering &TLI = IS->getTargetLowering();
if (TLI.getSchedulingPreference() == TargetLowering::SchedulingForLatency) {
- return createTDListDAGScheduler(IS, DAG, BB, Fast);
+ return createTDListDAGScheduler(IS, DAG, TM, BB, Fast);
} else {
assert(TLI.getSchedulingPreference() ==
TargetLowering::SchedulingForRegPressure && "Unknown sched type!");
- return createBURRListDAGScheduler(IS, DAG, BB, Fast);
+ return createBURRListDAGScheduler(IS, DAG, TM, BB, Fast);
}
}
}
@@ -1053,7 +1054,8 @@ ScheduleDAG *SelectionDAGISel::Schedule() {
RegisterScheduler::setDefault(Ctor);
}
- ScheduleDAG *Scheduler = Ctor(this, CurDAG, BB, Fast);
+ TargetMachine &TM = getTargetLowering().getTargetMachine();
+ ScheduleDAG *Scheduler = Ctor(this, CurDAG, &TM, BB, Fast);
Scheduler->Run();
return Scheduler;