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Diffstat (limited to 'lib/CodeGen/SelectionDAG/SelectionDAG.cpp')
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp7
1 files changed, 0 insertions, 7 deletions
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index ab6af1b4d1..8b353a28b6 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -928,13 +928,6 @@ SDValue SelectionDAG::getConstant(const ConstantInt &Val, EVT VT, bool isT) {
assert(Val.getBitWidth() == EltVT.getSizeInBits() &&
"APInt size does not match type size!");
- // In some cases the vector type is legal but the element type is illegal.
- // In this case, promote the inserted value. The type does not need to match
- // the vector element type. Any extra bits introduced will be
- // truncated away.
- if (VT.isVector())
- EltVT = TLI.getTypeToTransformTo(*getContext(), EltVT);
-
unsigned Opc = isT ? ISD::TargetConstant : ISD::Constant;
FoldingSetNodeID ID;
AddNodeIDNode(ID, Opc, getVTList(EltVT), 0, 0);