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diff --git a/docs/CommandGuide/man/man1/llc.1 b/docs/CommandGuide/man/man1/llc.1 new file mode 100644 index 0000000000..81832b10a6 --- /dev/null +++ b/docs/CommandGuide/man/man1/llc.1 @@ -0,0 +1,277 @@ +.\" Automatically generated by Pod::Man v1.37, Pod::Parser v1.14 +.\" +.\" Standard preamble: +.\" ======================================================================== +.de Sh \" Subsection heading +.br +.if t .Sp +.ne 5 +.PP +\fB\\$1\fR +.PP +.. +.de Sp \" Vertical space (when we can't use .PP) +.if t .sp .5v +.if n .sp +.. +.de Vb \" Begin verbatim text +.ft CW +.nf +.ne \\$1 +.. +.de Ve \" End verbatim text +.ft R +.fi +.. +.\" Set up some character translations and predefined strings. \*(-- will +.\" give an unbreakable dash, \*(PI will give pi, \*(L" will give a left +.\" double quote, and \*(R" will give a right double quote. | will give a +.\" real vertical bar. \*(C+ will give a nicer C++. Capital omega is used to +.\" do unbreakable dashes and therefore won't be available. \*(C` and \*(C' +.\" expand to `' in nroff, nothing in troff, for use with C<>. +.tr \(*W-|\(bv\*(Tr +.ds C+ C\v'-.1v'\h'-1p'\s-2+\h'-1p'+\s0\v'.1v'\h'-1p' +.ie n \{\ +. ds -- \(*W- +. ds PI pi +. if (\n(.H=4u)&(1m=24u) .ds -- \(*W\h'-12u'\(*W\h'-12u'-\" diablo 10 pitch +. if (\n(.H=4u)&(1m=20u) .ds -- \(*W\h'-12u'\(*W\h'-8u'-\" diablo 12 pitch +. ds L" "" +. ds R" "" +. ds C` "" +. ds C' "" +'br\} +.el\{\ +. ds -- \|\(em\| +. ds PI \(*p +. ds L" `` +. ds R" '' +'br\} +.\" +.\" If the F register is turned on, we'll generate index entries on stderr for +.\" titles (.TH), headers (.SH), subsections (.Sh), items (.Ip), and index +.\" entries marked with X<> in POD. Of course, you'll have to process the +.\" output yourself in some meaningful fashion. +.if \nF \{\ +. de IX +. tm Index:\\$1\t\\n%\t"\\$2" +.. +. nr % 0 +. rr F +.\} +.\" +.\" For nroff, turn off justification. Always turn off hyphenation; it makes +.\" way too many mistakes in technical documents. +.hy 0 +.if n .na +.\" +.\" Accent mark definitions (@(#)ms.acc 1.5 88/02/08 SMI; from UCB 4.2). +.\" Fear. Run. Save yourself. No user-serviceable parts. +. \" fudge factors for nroff and troff +.if n \{\ +. ds #H 0 +. ds #V .8m +. ds #F .3m +. ds #[ \f1 +. ds #] \fP +.\} +.if t \{\ +. ds #H ((1u-(\\\\n(.fu%2u))*.13m) +. ds #V .6m +. ds #F 0 +. ds #[ \& +. ds #] \& +.\} +. \" simple accents for nroff and troff +.if n \{\ +. ds ' \& +. ds ` \& +. ds ^ \& +. ds , \& +. ds ~ ~ +. ds / +.\} +.if t \{\ +. ds ' \\k:\h'-(\\n(.wu*8/10-\*(#H)'\'\h"|\\n:u" +. ds ` \\k:\h'-(\\n(.wu*8/10-\*(#H)'\`\h'|\\n:u' +. ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'^\h'|\\n:u' +. ds , \\k:\h'-(\\n(.wu*8/10)',\h'|\\n:u' +. ds ~ \\k:\h'-(\\n(.wu-\*(#H-.1m)'~\h'|\\n:u' +. ds / \\k:\h'-(\\n(.wu*8/10-\*(#H)'\z\(sl\h'|\\n:u' +.\} +. \" troff and (daisy-wheel) nroff accents +.ds : \\k:\h'-(\\n(.wu*8/10-\*(#H+.1m+\*(#F)'\v'-\*(#V'\z.\h'.2m+\*(#F'.\h'|\\n:u'\v'\*(#V' +.ds 8 \h'\*(#H'\(*b\h'-\*(#H' +.ds o \\k:\h'-(\\n(.wu+\w'\(de'u-\*(#H)/2u'\v'-.3n'\*(#[\z\(de\v'.3n'\h'|\\n:u'\*(#] +.ds d- \h'\*(#H'\(pd\h'-\w'~'u'\v'-.25m'\f2\(hy\fP\v'.25m'\h'-\*(#H' +.ds D- D\\k:\h'-\w'D'u'\v'-.11m'\z\(hy\v'.11m'\h'|\\n:u' +.ds th \*(#[\v'.3m'\s+1I\s-1\v'-.3m'\h'-(\w'I'u*2/3)'\s-1o\s+1\*(#] +.ds Th \*(#[\s+2I\s-2\h'-\w'I'u*3/5'\v'-.3m'o\v'.3m'\*(#] +.ds ae a\h'-(\w'a'u*4/10)'e +.ds Ae A\h'-(\w'A'u*4/10)'E +. \" corrections for vroff +.if v .ds ~ \\k:\h'-(\\n(.wu*9/10-\*(#H)'\s-2\u~\d\s+2\h'|\\n:u' +.if v .ds ^ \\k:\h'-(\\n(.wu*10/11-\*(#H)'\v'-.4m'^\v'.4m'\h'|\\n:u' +. \" for low resolution devices (crt and lpr) +.if \n(.H>23 .if \n(.V>19 \ +\{\ +. ds : e +. ds 8 ss +. ds o a +. ds d- d\h'-1'\(ga +. ds D- D\h'-1'\(hy +. ds th \o'bp' +. ds Th \o'LP' +. ds ae ae +. ds Ae AE +.\} +.rm #[ #] #H #V #F C +.\" ======================================================================== +.\" +.IX Title "LLC 1" +.TH LLC 1 "2006-03-13" "CVS" "LLVM Command Guide" +.SH "NAME" +llc \- LLVM static compiler +.SH "SYNOPSIS" +.IX Header "SYNOPSIS" +\&\fBllc\fR [\fIoptions\fR] [\fIfilename\fR] +.SH "DESCRIPTION" +.IX Header "DESCRIPTION" +The \fBllc\fR command compiles \s-1LLVM\s0 bytecode into assembly language for a +specified architecture. The assembly language output can then be passed through +a native assembler and linker to generate a native executable. +.PP +The choice of architecture for the output assembly code is automatically +determined from the input bytecode file, unless the \fB\-march\fR option is used to +override the default. +.SH "OPTIONS" +.IX Header "OPTIONS" +If \fIfilename\fR is \- or omitted, \fBllc\fR reads \s-1LLVM\s0 bytecode from standard input. +Otherwise, it will read \s-1LLVM\s0 bytecode from \fIfilename\fR. +.PP +If the \fB\-o\fR option is omitted, then \fBllc\fR will send its output to standard +output if the input is from standard input. If the \fB\-o\fR option specifies \-, +then the output will also be sent to standard output. +.PP +If no \fB\-o\fR option is specified and an input file other than \- is specified, +then \fBllc\fR creates the output filename by taking the input filename, +removing any existing \fI.bc\fR extension, and adding a \fI.s\fR suffix. +.PP +Other \fBllc\fR options are as follows: +.Sh "End-user Options" +.IX Subsection "End-user Options" +.IP "\fB\-\-help\fR" 4 +.IX Item "--help" +Print a summary of command line options. +.IP "\fB\-f\fR" 4 +.IX Item "-f" +Overwrite output files. By default, \fBllc\fR will refuse to overwrite +an output file which already exists. +.IP "\fB\-mtriple\fR=\fItarget triple\fR" 4 +.IX Item "-mtriple=target triple" +Override the target triple specified in the input bytecode file with the +specified string. +.IP "\fB\-march\fR=\fIarch\fR" 4 +.IX Item "-march=arch" +Specify the architecture for which to generate assembly, overriding the target +encoded in the bytecode file. See the output of \fBllc \-\-help\fR for a list of +valid architectures. By default this is inferred from the target triple or +autodetected to the current architecture. +.IP "\fB\-mcpu\fR=\fIcpuname\fR" 4 +.IX Item "-mcpu=cpuname" +Specify a specific chip in the current architecture to generate code for. +By default this is inferred from the target triple and autodetected to +the current architecture. For a list of available CPUs, use: +\&\fBllvm-as < /dev/null | llc \-march=xyz \-mcpu=help\fR +.IP "\fB\-mattr\fR=\fIa1,+a2,\-a3,...\fR" 4 +.IX Item "-mattr=a1,+a2,-a3,..." +Override or control specific attributes of the target, such as whether \s-1SIMD\s0 +operations are enabled or not. The default set of attributes is set by the +current \s-1CPU\s0. For a list of available attributes, use: +\&\fBllvm-as < /dev/null | llc \-march=xyz \-mattr=help\fR +.IP "\fB\-\-disable\-fp\-elim\fR" 4 +.IX Item "--disable-fp-elim" +Disable frame pointer elimination optimization. +.IP "\fB\-\-disable\-excess\-fp\-precision\fR" 4 +.IX Item "--disable-excess-fp-precision" +Disable optimizations that may produce excess precision for floating point. +Note that this option can dramatically slow down code on some systems +(e.g. X86). +.IP "\fB\-\-enable\-unsafe\-fp\-math\fR" 4 +.IX Item "--enable-unsafe-fp-math" +Enable optimizations that make unsafe assumptions about \s-1IEEE\s0 math (e.g. that +addition is associative) or may not work for all input ranges. These +optimizations allow the code generator to make use of some instructions which +would otherwise not be usable (such as fsin on X86). +.IP "\fB\-\-enable\-correct\-eh\-support\fR" 4 +.IX Item "--enable-correct-eh-support" +Instruct the \fBlowerinvoke\fR pass to insert code for correct exception handling +support. This is expensive and is by default omitted for efficiency. +.IP "\fB\-\-stats\fR" 4 +.IX Item "--stats" +Print statistics recorded by code-generation passes. +.IP "\fB\-\-time\-passes\fR" 4 +.IX Item "--time-passes" +Record the amount of time needed for each pass and print a report to standard +error. +.IP "\fB\-\-load\fR=\fIdso_path\fR" 4 +.IX Item "--load=dso_path" +Dynamically load \fIdso_path\fR (a path to a dynamically shared object) that +implements an \s-1LLVM\s0 target. This will permit the target name to be used with the +\&\fB\-march\fR option so that code can be generated for that target. +.Sh "Tuning/Configuration Options" +.IX Subsection "Tuning/Configuration Options" +.IP "\fB\-\-print\-machineinstrs\fR" 4 +.IX Item "--print-machineinstrs" +Print generated machine code between compilation phases (useful for debugging). +.IP "\fB\-\-regalloc\fR=\fIallocator\fR" 4 +.IX Item "--regalloc=allocator" +Specify the register allocator to use. The default \fIallocator\fR is \fIlocal\fR. +Valid register allocators are: +.RS 4 +.IP "\fIsimple\fR" 4 +.IX Item "simple" +Very simple \*(L"always spill\*(R" register allocator +.IP "\fIlocal\fR" 4 +.IX Item "local" +Local register allocator +.IP "\fIlinearscan\fR" 4 +.IX Item "linearscan" +Linear scan global register allocator +.IP "\fIiterativescan\fR" 4 +.IX Item "iterativescan" +Iterative scan global register allocator +.RE +.RS 4 +.RE +.IP "\fB\-\-spiller\fR=\fIspiller\fR" 4 +.IX Item "--spiller=spiller" +Specify the spiller to use for register allocators that support it. Currently +this option is used only by the linear scan register allocator. The default +\&\fIspiller\fR is \fIlocal\fR. Valid spillers are: +.RS 4 +.IP "\fIsimple\fR" 4 +.IX Item "simple" +Simple spiller +.IP "\fIlocal\fR" 4 +.IX Item "local" +Local spiller +.RE +.RS 4 +.RE +.Sh "Intel IA\-32\-specific Options" +.IX Subsection "Intel IA-32-specific Options" +.IP "\fB\-\-x86\-asm\-syntax=att|intel\fR" 4 +.IX Item "--x86-asm-syntax=att|intel" +Specify whether to emit assembly code in \s-1AT&T\s0 syntax (the default) or intel +syntax. +.SH "EXIT STATUS" +.IX Header "EXIT STATUS" +If \fBllc\fR succeeds, it will exit with 0. Otherwise, if an error occurs, +it will exit with a non-zero value. +.SH "SEE ALSO" +.IX Header "SEE ALSO" +lli +.SH "AUTHORS" +.IX Header "AUTHORS" +Maintained by the \s-1LLVM\s0 Team (<http://llvm.org>). |