diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCFrameInfo.h | 20 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCRegisterInfo.cpp | 3 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/Frames-alloca.ll | 20 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/Frames-large.ll | 10 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/Frames-small.ll | 20 | ||||
| -rw-r--r-- | test/CodeGen/PowerPC/ppc-prologue.ll | 2 |
6 files changed, 43 insertions, 32 deletions
diff --git a/lib/Target/PowerPC/PPCFrameInfo.h b/lib/Target/PowerPC/PPCFrameInfo.h index 65f113e6fb..4bf543a8d0 100644 --- a/lib/Target/PowerPC/PPCFrameInfo.h +++ b/lib/Target/PowerPC/PPCFrameInfo.h @@ -42,11 +42,12 @@ public: /// frame pointer. static unsigned getFramePointerSaveOffset(bool isPPC64, bool isDarwinABI) { // For the Darwin ABI: - // Use the TOC save slot in the PowerPC linkage area for saving the frame - // pointer (if needed.) LLVM does not generate code that uses the TOC (R2 - // is treated as a caller saved register.) + // We cannot use the TOC save slot (offset +20) in the PowerPC linkage area + // for saving the frame pointer (if needed.) While the published ABI has + // not used this slot since at least MacOSX 10.2, there is older code + // around that does use it, and that needs to continue to work. if (isDarwinABI) - return isPPC64 ? 40 : 20; + return isPPC64 ? -8U : -4U; // SVR4 ABI: First slot in the general register save area. return -4U; @@ -90,6 +91,17 @@ public: // With the SVR4 ABI, callee-saved registers have fixed offsets on the stack. const SpillSlot * getCalleeSavedSpillSlots(unsigned &NumEntries) const { + if (TM.getSubtarget<PPCSubtarget>().isDarwinABI()) { + NumEntries = 1; + if (TM.getSubtarget<PPCSubtarget>().isPPC64()) { + static const SpillSlot darwin64Offsets[] = {PPC::X31, -8}; + return darwin64Offsets; + } else { + static const SpillSlot darwinOffsets[] = {PPC::R31, -4}; + return darwinOffsets; + } + } + // Early exit if not using the SVR4 ABI. if (!TM.getSubtarget<PPCSubtarget>().isSVR4ABI()) { NumEntries = 0; diff --git a/lib/Target/PowerPC/PPCRegisterInfo.cpp b/lib/Target/PowerPC/PPCRegisterInfo.cpp index 9a1a00f462..0c3c8eb649 100644 --- a/lib/Target/PowerPC/PPCRegisterInfo.cpp +++ b/lib/Target/PowerPC/PPCRegisterInfo.cpp @@ -1033,12 +1033,11 @@ PPCRegisterInfo::processFunctionBeforeCalleeSavedScan(MachineFunction &MF, // Save R31 if necessary int FPSI = FI->getFramePointerSaveIndex(); bool isPPC64 = Subtarget.isPPC64(); - bool isSVR4ABI = Subtarget.isSVR4ABI(); bool isDarwinABI = Subtarget.isDarwinABI(); MachineFrameInfo *MFI = MF.getFrameInfo(); // If the frame pointer save index hasn't been defined yet. - if (!FPSI && needsFP(MF) && isSVR4ABI) { + if (!FPSI && needsFP(MF)) { // Find out what the fix offset of the frame pointer save area. int FPOffset = PPCFrameInfo::getFramePointerSaveOffset(isPPC64, isDarwinABI); diff --git a/test/CodeGen/PowerPC/Frames-alloca.ll b/test/CodeGen/PowerPC/Frames-alloca.ll index 25fc626550..aed4fdbb2d 100644 --- a/test/CodeGen/PowerPC/Frames-alloca.ll +++ b/test/CodeGen/PowerPC/Frames-alloca.ll @@ -6,23 +6,23 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim -enable-ppc32-regscavenger | FileCheck %s -check-prefix=PPC32-RS-NOFP -; CHECK-PPC32: stw r31, 20(r1) +; CHECK-PPC32: stw r31, -4(r1) ; CHECK-PPC32: lwz r1, 0(r1) -; CHECK-PPC32: lwz r31, 20(r1) -; CHECK-PPC32-NOFP: stw r31, 20(r1) +; CHECK-PPC32: lwz r31, -4(r1) +; CHECK-PPC32-NOFP: stw r31, -4(r1) ; CHECK-PPC32-NOFP: lwz r1, 0(r1) -; CHECK-PPC32-NOFP: lwz r31, 20(r1) +; CHECK-PPC32-NOFP: lwz r31, -4(r1) ; CHECK-PPC32-RS: stwu r1, -80(r1) ; CHECK-PPC32-RS-NOFP: stwu r1, -80(r1) -; CHECK-PPC64: std r31, 40(r1) -; CHECK-PPC64: stdu r1, -112(r1) +; CHECK-PPC64: std r31, -8(r1) +; CHECK-PPC64: stdu r1, -128(r1) ; CHECK-PPC64: ld r1, 0(r1) -; CHECK-PPC64: ld r31, 40(r1) -; CHECK-PPC64-NOFP: std r31, 40(r1) -; CHECK-PPC64-NOFP: stdu r1, -112(r1) +; CHECK-PPC64: ld r31, -8(r1) +; CHECK-PPC64-NOFP: std r31, -8(r1) +; CHECK-PPC64-NOFP: stdu r1, -128(r1) ; CHECK-PPC64-NOFP: ld r1, 0(r1) -; CHECK-PPC64-NOFP: ld r31, 40(r1) +; CHECK-PPC64-NOFP: ld r31, -8(r1) define i32* @f1(i32 %n) { %tmp = alloca i32, i32 %n ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/Frames-large.ll b/test/CodeGen/PowerPC/Frames-large.ll index fda2e4ff9c..302d3df284 100644 --- a/test/CodeGen/PowerPC/Frames-large.ll +++ b/test/CodeGen/PowerPC/Frames-large.ll @@ -22,13 +22,13 @@ define i32* @f1() nounwind { ; PPC32-NOFP: blr ; PPC32-FP: _f1: -; PPC32-FP: stw r31, 20(r1) +; PPC32-FP: stw r31, -4(r1) ; PPC32-FP: lis r0, -1 ; PPC32-FP: ori r0, r0, 32704 ; PPC32-FP: stwux r1, r1, r0 ; ... ; PPC32-FP: lwz r1, 0(r1) -; PPC32-FP: lwz r31, 20(r1) +; PPC32-FP: lwz r31, -4(r1) ; PPC32-FP: blr @@ -42,11 +42,11 @@ define i32* @f1() nounwind { ; PPC64-FP: _f1: -; PPC64-FP: std r31, 40(r1) +; PPC64-FP: std r31, -8(r1) ; PPC64-FP: lis r0, -1 -; PPC64-FP: ori r0, r0, 32656 +; PPC64-FP: ori r0, r0, 32640 ; PPC64-FP: stdux r1, r1, r0 ; ... ; PPC64-FP: ld r1, 0(r1) -; PPC64-FP: ld r31, 40(r1) +; PPC64-FP: ld r31, -8(r1) ; PPC64-FP: blr diff --git a/test/CodeGen/PowerPC/Frames-small.ll b/test/CodeGen/PowerPC/Frames-small.ll index 6875704cf3..404fdd0196 100644 --- a/test/CodeGen/PowerPC/Frames-small.ll +++ b/test/CodeGen/PowerPC/Frames-small.ll @@ -1,26 +1,26 @@ ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -o %t1 -; RUN not grep {stw r31, 20(r1)} %t1 +; RUN not grep {stw r31, -4(r1)} %t1 ; RUN: grep {stwu r1, -16448(r1)} %t1 ; RUN: grep {addi r1, r1, 16448} %t1 ; RUN: llc < %s -march=ppc32 | \ -; RUN: not grep {lwz r31, 20(r1)} +; RUN: not grep {lwz r31, -4(r1)} ; RUN: llc < %s -march=ppc32 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ ; RUN: -o %t2 -; RUN: grep {stw r31, 20(r1)} %t2 +; RUN: grep {stw r31, -4(r1)} %t2 ; RUN: grep {stwu r1, -16448(r1)} %t2 ; RUN: grep {addi r1, r1, 16448} %t2 -; RUN: grep {lwz r31, 20(r1)} %t2 +; RUN: grep {lwz r31, -4(r1)} %t2 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -o %t3 -; RUN: not grep {std r31, 40(r1)} %t3 +; RUN: not grep {std r31, -8(r1)} %t3 ; RUN: grep {stdu r1, -16496(r1)} %t3 ; RUN: grep {addi r1, r1, 16496} %t3 -; RUN: not grep {ld r31, 40(r1)} %t3 +; RUN: not grep {ld r31, -8(r1)} %t3 ; RUN: llc < %s -march=ppc64 -mtriple=powerpc-apple-darwin8 -disable-fp-elim \ ; RUN: -o %t4 -; RUN: grep {std r31, 40(r1)} %t4 -; RUN: grep {stdu r1, -16496(r1)} %t4 -; RUN: grep {addi r1, r1, 16496} %t4 -; RUN: grep {ld r31, 40(r1)} %t4 +; RUN: grep {std r31, -8(r1)} %t4 +; RUN: grep {stdu r1, -16512(r1)} %t4 +; RUN: grep {addi r1, r1, 16512} %t4 +; RUN: grep {ld r31, -8(r1)} %t4 define i32* @f1() { %tmp = alloca i32, i32 4095 ; <i32*> [#uses=1] diff --git a/test/CodeGen/PowerPC/ppc-prologue.ll b/test/CodeGen/PowerPC/ppc-prologue.ll index 581d010a90..e49dcb82c6 100644 --- a/test/CodeGen/PowerPC/ppc-prologue.ll +++ b/test/CodeGen/PowerPC/ppc-prologue.ll @@ -2,7 +2,7 @@ define i32 @_Z4funci(i32 %a) ssp { ; CHECK: mflr r0 -; CHECK-NEXT: stw r31, 20(r1) +; CHECK-NEXT: stw r31, -4(r1) ; CHECK-NEXT: stw r0, 8(r1) ; CHECK-NEXT: stwu r1, -80(r1) ; CHECK-NEXT: Llabel1: |