diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCISelLowering.cpp | 12 |
1 files changed, 9 insertions, 3 deletions
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp index 7eb6bec28f..35cf10a4c0 100644 --- a/lib/Target/PowerPC/PPCISelLowering.cpp +++ b/lib/Target/PowerPC/PPCISelLowering.cpp @@ -876,9 +876,6 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, SDOperand Ptr; if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { Ptr = LD->getBasePtr(); - - // FIXME: PPC has no LWAU! - } else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) { ST = ST; //Ptr = ST->getBasePtr(); @@ -891,6 +888,15 @@ bool PPCTargetLowering::getPreIndexedAddressParts(SDNode *N, SDOperand &Base, // TODO: Handle reg+reg. if (!SelectAddressRegImm(Ptr, Offset, Base, DAG)) return false; + + // PPC64 doesn't have lwau, but it does have lwaux. Reject preinc load of + // sext i32 to i64 when addr mode is r+i. + if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) { + if (LD->getValueType(0) == MVT::i64 && LD->getLoadedVT() == MVT::i32 && + LD->getExtensionType() == ISD::SEXTLOAD && + isa<ConstantSDNode>(Offset)) + return false; + } AM = ISD::PRE_INC; return true; |