diff options
| -rw-r--r-- | lib/Target/Mips/Mips64InstrInfo.td | 5 | ||||
| -rw-r--r-- | test/CodeGen/Mips/mips64ext.ll | 8 |
2 files changed, 13 insertions, 0 deletions
diff --git a/lib/Target/Mips/Mips64InstrInfo.td b/lib/Target/Mips/Mips64InstrInfo.td index c58eade471..681c7ae1bc 100644 --- a/lib/Target/Mips/Mips64InstrInfo.td +++ b/lib/Target/Mips/Mips64InstrInfo.td @@ -215,6 +215,8 @@ def DSLL64_32 : FR<0x3c, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), def SLL64_32 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPURegs:$rt), "sll\t$rd, $rt, 0", [], IIAlu>; +def SLL64_64 : FR<0x0, 0x00, (outs CPU64Regs:$rd), (ins CPU64Regs:$rt), + "sll\t$rd, $rt, 0", [], IIAlu>; //===----------------------------------------------------------------------===// // Arbitrary patterns that map to one or more instructions @@ -311,3 +313,6 @@ def : Pat<(i64 (anyext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; def : Pat<(i64 (zext CPURegs:$src)), (DSRL (DSLL64_32 CPURegs:$src), 32)>; def : Pat<(i64 (sext CPURegs:$src)), (SLL64_32 CPURegs:$src)>; +// Sign extend in register +def : Pat<(i64 (sext_inreg CPU64Regs:$src, i32)), (SLL64_64 CPU64Regs:$src)>; + diff --git a/test/CodeGen/Mips/mips64ext.ll b/test/CodeGen/Mips/mips64ext.ll index ae6078b829..7981ec7a47 100644 --- a/test/CodeGen/Mips/mips64ext.ll +++ b/test/CodeGen/Mips/mips64ext.ll @@ -9,3 +9,11 @@ entry: %conv = zext i32 %add to i64 ret i64 %conv } + +define i64 @sext64_32(i32 %a) nounwind readnone { +entry: +; CHECK: sll ${{[0-9]+}}, ${{[0-9]+}}, 0 + %conv = sext i32 %a to i64 + ret i64 %conv +} + |