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-rw-r--r--lib/CodeGen/MachineVerifier.cpp11
-rw-r--r--lib/CodeGen/RegisterScavenging.cpp4
-rw-r--r--test/CodeGen/X86/vector.ll2
3 files changed, 12 insertions, 5 deletions
diff --git a/lib/CodeGen/MachineVerifier.cpp b/lib/CodeGen/MachineVerifier.cpp
index 8541d18ef3..f798c1346e 100644
--- a/lib/CodeGen/MachineVerifier.cpp
+++ b/lib/CodeGen/MachineVerifier.cpp
@@ -664,8 +664,15 @@ MachineVerifier::visitMachineOperand(const MachineOperand *MO, unsigned MONum) {
// Use of a dead register.
if (!regsLive.count(Reg)) {
if (TargetRegisterInfo::isPhysicalRegister(Reg)) {
- // Reserved registers may be used even when 'dead'.
- if (!isReserved(Reg))
+ // Reserved registers may be used even when 'dead', but allocatable
+ // registers can't.
+ // We track the liveness of unreserved, unallocatable registers while
+ // the machine function is still in SSA form. That lets us check for
+ // bad EFLAGS uses. After register allocation, the unallocatable
+ // registers are probably quite wrong. For example, the x87 ST0-ST7
+ // registers don't track liveness at all.
+ if (!isReserved(Reg) &&
+ (MRI->isSSA() || TRI->isInAllocatableClass(Reg)))
report("Using an undefined physical register", MO, MONum);
} else {
BBInfo &MInfo = MBBInfoMap[MI->getParent()];
diff --git a/lib/CodeGen/RegisterScavenging.cpp b/lib/CodeGen/RegisterScavenging.cpp
index 9e9a145b0a..4fc711e1b8 100644
--- a/lib/CodeGen/RegisterScavenging.cpp
+++ b/lib/CodeGen/RegisterScavenging.cpp
@@ -157,7 +157,7 @@ void RegScavenger::forward() {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
- if (!Reg || isReserved(Reg))
+ if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
continue;
if (MO.isUse()) {
@@ -184,7 +184,7 @@ void RegScavenger::forward() {
if (!MO.isReg())
continue;
unsigned Reg = MO.getReg();
- if (!Reg || isReserved(Reg))
+ if (!Reg || isReserved(Reg) || !TRI->isInAllocatableClass(Reg))
continue;
if (MO.isUse()) {
if (MO.isUndef())
diff --git a/test/CodeGen/X86/vector.ll b/test/CodeGen/X86/vector.ll
index 46b0e1890f..4268d02c5a 100644
--- a/test/CodeGen/X86/vector.ll
+++ b/test/CodeGen/X86/vector.ll
@@ -1,6 +1,6 @@
; Test that vectors are scalarized/lowered correctly.
; RUN: llc < %s -march=x86 -mcpu=i386 > %t
-; RUN: llc < %s -march=x86 -mcpu=yonah >> %t
+; RUN: llc < %s -march=x86 -mcpu=yonah -verify-machineinstrs >> %t
%d8 = type <8 x double>
%f1 = type <1 x float>