diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrFormats.td | 6 | ||||
| -rw-r--r-- | lib/Target/ARM/ARMInstrThumb2.td | 48 | ||||
| -rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 6 |
3 files changed, 33 insertions, 27 deletions
diff --git a/lib/Target/ARM/ARMInstrFormats.td b/lib/Target/ARM/ARMInstrFormats.td index b51887d41a..9387cf0ab1 100644 --- a/lib/Target/ARM/ARMInstrFormats.td +++ b/lib/Target/ARM/ARMInstrFormats.td @@ -1207,7 +1207,7 @@ class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, bits<4> Rt; bits<4> Rn; - bits<9> addr; + bits<9> offset; let Inst{31-27} = 0b11111; let Inst{26-25} = 0b00; let Inst{24} = signed; @@ -1219,9 +1219,9 @@ class T2Ipostldst<bit signed, bits<2> opcod, bit load, bit pre, let Inst{11} = 1; // (P, W) = (1, 1) Pre-indexed or (0, 1) Post-indexed let Inst{10} = pre; // The P bit. - let Inst{9} = addr{8}; // Sign bit + let Inst{9} = offset{8}; // Sign bit let Inst{8} = 1; // The W bit. - let Inst{7-0} = addr{7-0}; + let Inst{7-0} = offset{7-0}; } // Tv5Pat - Same as Pat<>, but requires V5T Thumb mode. diff --git a/lib/Target/ARM/ARMInstrThumb2.td b/lib/Target/ARM/ARMInstrThumb2.td index 340c023c37..3e64c1905c 100644 --- a/lib/Target/ARM/ARMInstrThumb2.td +++ b/lib/Target/ARM/ARMInstrThumb2.td @@ -1253,9 +1253,9 @@ def t2LDR_PRE : T2Ipreldst<0, 0b10, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), } def t2LDR_POST : T2Ipostldst<0, 0b10, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), - (ins GPR:$Rn, t2am_imm8_offset:$addr), - AddrModeT2_i8, IndexModePost, IIC_iLoad_iu, - "ldr", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>; + (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), + AddrModeT2_i8, IndexModePost, IIC_iLoad_iu, + "ldr", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>; def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins t2addrmode_imm8:$addr), @@ -1265,9 +1265,9 @@ def t2LDRB_PRE : T2Ipreldst<0, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; } def t2LDRB_POST : T2Ipostldst<0, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), - (ins GPR:$Rn, t2am_imm8_offset:$addr), - AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, - "ldrb", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>; + (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), + AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, + "ldrb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>; def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins t2addrmode_imm8:$addr), @@ -1277,9 +1277,9 @@ def t2LDRH_PRE : T2Ipreldst<0, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; } def t2LDRH_POST : T2Ipostldst<0, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), - (ins GPR:$Rn, t2am_imm8_offset:$addr), - AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, - "ldrh", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>; + (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), + AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, + "ldrh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>; def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins t2addrmode_imm8:$addr), @@ -1289,9 +1289,9 @@ def t2LDRSB_PRE : T2Ipreldst<1, 0b00, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; } def t2LDRSB_POST : T2Ipostldst<1, 0b00, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), - (ins GPR:$Rn, t2am_imm8_offset:$addr), - AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, - "ldrsb", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>; + (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), + AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, + "ldrsb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>; def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), (ins t2addrmode_imm8:$addr), @@ -1301,9 +1301,9 @@ def t2LDRSH_PRE : T2Ipreldst<1, 0b01, 1, 1, (outs GPR:$Rt, GPR:$Rn_wb), let AsmMatchConverter = "cvtLdWriteBackRegT2AddrModeImm8"; } def t2LDRSH_POST : T2Ipostldst<1, 0b01, 1, 0, (outs GPR:$Rt, GPR:$Rn_wb), - (ins GPR:$Rn, t2am_imm8_offset:$addr), - AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, - "ldrsh", "\t$Rt, [$Rn], $addr", "$Rn = $Rn_wb", []>; + (ins addr_offset_none:$Rn, t2am_imm8_offset:$offset), + AddrModeT2_i8, IndexModePost, IIC_iLoad_bh_iu, + "ldrsh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb", []>; } // mayLoad = 1, neverHasSideEffects = 1 // LDRT, LDRBT, LDRHT, LDRSBT, LDRSHT all have offset mode (PUW=0b110). @@ -1356,12 +1356,12 @@ def t2STR_PRE : T2Ipreldst<0, 0b10, 0, 1, (outs GPRnopc:$Rn_wb), (pre_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; def t2STR_POST : T2Ipostldst<0, 0b10, 0, 0, (outs GPRnopc:$Rn_wb), - (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), + (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset), AddrModeT2_i8, IndexModePost, IIC_iStore_iu, - "str", "\t$Rt, [$Rn], $addr", + "str", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb,@earlyclobber $Rn_wb", [(set GPRnopc:$Rn_wb, - (post_store rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; + (post_store rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>; def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb), (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), @@ -1372,12 +1372,12 @@ def t2STRH_PRE : T2Ipreldst<0, 0b01, 0, 1, (outs GPRnopc:$Rn_wb), (pre_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; def t2STRH_POST : T2Ipostldst<0, 0b01, 0, 0, (outs GPRnopc:$Rn_wb), - (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), + (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset), AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, - "strh", "\t$Rt, [$Rn], $addr", + "strh", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb,@earlyclobber $Rn_wb", [(set GPRnopc:$Rn_wb, - (post_truncsti16 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; + (post_truncsti16 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>; def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb), (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), @@ -1388,12 +1388,12 @@ def t2STRB_PRE : T2Ipreldst<0, 0b00, 0, 1, (outs GPRnopc:$Rn_wb), (pre_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; def t2STRB_POST : T2Ipostldst<0, 0b00, 0, 0, (outs GPRnopc:$Rn_wb), - (ins rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr), + (ins rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset), AddrModeT2_i8, IndexModePost, IIC_iStore_bh_iu, - "strb", "\t$Rt, [$Rn], $addr", + "strb", "\t$Rt, $Rn, $offset", "$Rn = $Rn_wb,@earlyclobber $Rn_wb", [(set GPRnopc:$Rn_wb, - (post_truncsti8 rGPR:$Rt, GPRnopc:$Rn, t2am_imm8_offset:$addr))]>; + (post_truncsti8 rGPR:$Rt, addr_offset_none:$Rn, t2am_imm8_offset:$offset))]>; // STRT, STRBT, STRHT all have offset mode (PUW=0b110) and are for disassembly // only. diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index c88eb24f28..e97cc17885 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -551,6 +551,9 @@ _func: ldr r2, [r4, #255]! ldr r8, [sp, #4]! ldr lr, [sp, #-4]! + ldr r2, [r4], #255 + ldr r8, [sp], #4 + ldr lr, [sp], #-4 @ CHECK: ldr.w r1, [r8, r1] @ encoding: [0x58,0xf8,0x01,0x10] @ CHECK: ldr.w r4, [r5, r2] @ encoding: [0x55,0xf8,0x02,0x40] @@ -561,6 +564,9 @@ _func: @ CHECK: ldr r2, [r4, #255]! @ encoding: [0x54,0xf8,0xff,0x2f] @ CHECK: ldr r8, [sp, #4]! @ encoding: [0x5d,0xf8,0x04,0x8f] @ CHECK: ldr lr, [sp, #-4]! @ encoding: [0x5d,0xf8,0x04,0xed] +@ CHECK: ldr r2, [r4], #255 @ encoding: [0x54,0xf8,0xff,0x2b] +@ CHECK: ldr r8, [sp], #4 @ encoding: [0x5d,0xf8,0x04,0x8b] +@ CHECK: ldr lr, [sp], #-4 @ encoding: [0x5d,0xf8,0x04,0xe9] @------------------------------------------------------------------------------ |