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-rw-r--r--include/llvm/CodeGen/CallingConvLower.h40
-rw-r--r--include/llvm/CodeGen/DAGISelHeader.h2
-rw-r--r--include/llvm/CodeGen/FastISel.h44
-rw-r--r--include/llvm/CodeGen/RuntimeLibcalls.h12
-rw-r--r--include/llvm/CodeGen/SelectionDAG.h264
-rw-r--r--include/llvm/CodeGen/SelectionDAGISel.h2
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h100
-rw-r--r--include/llvm/CodeGen/ValueTypes.h80
-rw-r--r--include/llvm/Target/TargetLowering.h214
-rw-r--r--include/llvm/Target/TargetRegisterInfo.h14
-rw-r--r--include/llvm/Target/TargetSelectionDAG.td74
-rw-r--r--lib/CodeGen/SelectionDAG/CallingConvLower.cpp30
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp390
-rw-r--r--lib/CodeGen/SelectionDAG/FastISel.cpp90
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp372
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeFloatTypes.cpp206
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp270
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypes.cpp40
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypes.h28
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeTypesGeneric.cpp52
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp22
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp252
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGFast.cpp14
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp20
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp18
-rw-r--r--lib/CodeGen/SelectionDAG/ScheduleDAGSDNodesEmit.cpp18
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp476
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp820
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGBuild.h2
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGISel.cpp16
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAGPrinter.cpp8
-rw-r--r--lib/CodeGen/SelectionDAG/TargetLowering.cpp400
-rw-r--r--lib/Target/ARM/ARMISelDAGToDAG.cpp412
-rw-r--r--lib/Target/ARM/ARMISelLowering.cpp722
-rw-r--r--lib/Target/ARM/ARMISelLowering.h10
-rw-r--r--lib/Target/ARM/ARMInstrInfo.td8
-rw-r--r--lib/Target/ARM/ARMInstrNEON.td18
-rw-r--r--lib/Target/ARM/ARMInstrThumb.td8
-rw-r--r--lib/Target/ARM/ARMInstrThumb2.td8
-rw-r--r--lib/Target/ARM/Thumb1RegisterInfo.cpp2
-rw-r--r--lib/Target/ARM/Thumb1RegisterInfo.h2
-rw-r--r--lib/Target/Alpha/AlphaISelDAGToDAG.cpp54
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp332
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.h4
-rw-r--r--lib/Target/Blackfin/BlackfinISelDAGToDAG.cpp18
-rw-r--r--lib/Target/Blackfin/BlackfinISelLowering.cpp172
-rw-r--r--lib/Target/Blackfin/BlackfinISelLowering.h6
-rw-r--r--lib/Target/Blackfin/BlackfinInstrInfo.td8
-rw-r--r--lib/Target/Blackfin/BlackfinRegisterInfo.cpp4
-rw-r--r--lib/Target/Blackfin/BlackfinRegisterInfo.h2
-rw-r--r--lib/Target/CellSPU/SPUISelDAGToDAG.cpp238
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.cpp1028
-rw-r--r--lib/Target/CellSPU/SPUISelLowering.h18
-rw-r--r--lib/Target/CellSPU/SPUOperands.td68
-rw-r--r--lib/Target/MSP430/MSP430ISelDAGToDAG.cpp30
-rw-r--r--lib/Target/MSP430/MSP430ISelLowering.cpp156
-rw-r--r--lib/Target/Mips/MipsISelDAGToDAG.cpp48
-rw-r--r--lib/Target/Mips/MipsISelLowering.cpp272
-rw-r--r--lib/Target/Mips/MipsISelLowering.h6
-rw-r--r--lib/Target/Mips/MipsInstrInfo.td4
-rw-r--r--lib/Target/PIC16/PIC16ISelLowering.cpp398
-rw-r--r--lib/Target/PIC16/PIC16ISelLowering.h4
-rw-r--r--lib/Target/PowerPC/PPCISelDAGToDAG.cpp208
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp1018
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.h6
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.td6
-rw-r--r--lib/Target/Sparc/SparcISelDAGToDAG.cpp28
-rw-r--r--lib/Target/Sparc/SparcISelLowering.cpp368
-rw-r--r--lib/Target/Sparc/SparcISelLowering.h4
-rw-r--r--lib/Target/Sparc/SparcInstrInfo.td4
-rw-r--r--lib/Target/SystemZ/SystemZISelDAGToDAG.cpp54
-rw-r--r--lib/Target/SystemZ/SystemZISelLowering.cpp166
-rw-r--r--lib/Target/SystemZ/SystemZOperands.td4
-rw-r--r--lib/Target/TargetRegisterInfo.cpp6
-rw-r--r--lib/Target/X86/AsmPrinter/X86ATTAsmPrinter.cpp18
-rw-r--r--lib/Target/X86/AsmPrinter/X86ATTInstPrinter.cpp6
-rw-r--r--lib/Target/X86/AsmPrinter/X86IntelAsmPrinter.cpp14
-rw-r--r--lib/Target/X86/X86FastISel.cpp200
-rw-r--r--lib/Target/X86/X86ISelDAGToDAG.cpp166
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp2260
-rw-r--r--lib/Target/X86/X86ISelLowering.h38
-rw-r--r--lib/Target/X86/X86InstrInfo.cpp12
-rw-r--r--lib/Target/X86/X86RegisterInfo.cpp10
-rw-r--r--lib/Target/X86/X86RegisterInfo.h4
-rw-r--r--lib/Target/XCore/XCoreISelDAGToDAG.cpp46
-rw-r--r--lib/Target/XCore/XCoreISelLowering.cpp248
-rw-r--r--lib/Target/XCore/XCoreISelLowering.h2
-rw-r--r--lib/Transforms/Scalar/CodeGenPrepare.cpp4
-rw-r--r--lib/Transforms/Scalar/LoopStrengthReduce.cpp2
-rw-r--r--lib/VMCore/Function.cpp4
-rw-r--r--lib/VMCore/ValueTypes.cpp204
-rw-r--r--lib/VMCore/Verifier.cpp26
-rw-r--r--utils/TableGen/CallingConvEmitter.cpp12
-rw-r--r--utils/TableGen/CodeGenDAGPatterns.cpp172
-rw-r--r--utils/TableGen/CodeGenDAGPatterns.h28
-rw-r--r--utils/TableGen/CodeGenIntrinsics.h8
-rw-r--r--utils/TableGen/CodeGenRegisters.h6
-rw-r--r--utils/TableGen/CodeGenTarget.cpp112
-rw-r--r--utils/TableGen/CodeGenTarget.h20
-rw-r--r--utils/TableGen/DAGISelEmitter.cpp96
-rw-r--r--utils/TableGen/FastISelEmitter.cpp26
-rw-r--r--utils/TableGen/IntrinsicEmitter.cpp54
-rw-r--r--utils/TableGen/RegisterInfoEmitter.cpp4
-rw-r--r--utils/TableGen/TGValueTypes.cpp34
104 files changed, 7079 insertions, 7079 deletions
diff --git a/include/llvm/CodeGen/CallingConvLower.h b/include/llvm/CodeGen/CallingConvLower.h
index 02a2bf570e..eb9168707a 100644
--- a/include/llvm/CodeGen/CallingConvLower.h
+++ b/include/llvm/CodeGen/CallingConvLower.h
@@ -54,14 +54,14 @@ private:
LocInfo HTP : 6;
/// ValVT - The type of the value being assigned.
- MVT ValVT;
+ EVT ValVT;
/// LocVT - The type of the location being assigned to.
- MVT LocVT;
+ EVT LocVT;
public:
- static CCValAssign getReg(unsigned ValNo, MVT ValVT,
- unsigned RegNo, MVT LocVT,
+ static CCValAssign getReg(unsigned ValNo, EVT ValVT,
+ unsigned RegNo, EVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret.ValNo = ValNo;
@@ -74,8 +74,8 @@ public:
return Ret;
}
- static CCValAssign getCustomReg(unsigned ValNo, MVT ValVT,
- unsigned RegNo, MVT LocVT,
+ static CCValAssign getCustomReg(unsigned ValNo, EVT ValVT,
+ unsigned RegNo, EVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret = getReg(ValNo, ValVT, RegNo, LocVT, HTP);
@@ -83,8 +83,8 @@ public:
return Ret;
}
- static CCValAssign getMem(unsigned ValNo, MVT ValVT,
- unsigned Offset, MVT LocVT,
+ static CCValAssign getMem(unsigned ValNo, EVT ValVT,
+ unsigned Offset, EVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret.ValNo = ValNo;
@@ -97,8 +97,8 @@ public:
return Ret;
}
- static CCValAssign getCustomMem(unsigned ValNo, MVT ValVT,
- unsigned Offset, MVT LocVT,
+ static CCValAssign getCustomMem(unsigned ValNo, EVT ValVT,
+ unsigned Offset, EVT LocVT,
LocInfo HTP) {
CCValAssign Ret;
Ret = getMem(ValNo, ValVT, Offset, LocVT, HTP);
@@ -107,7 +107,7 @@ public:
}
unsigned getValNo() const { return ValNo; }
- MVT getValVT() const { return ValVT; }
+ EVT getValVT() const { return ValVT; }
bool isRegLoc() const { return !isMem; }
bool isMemLoc() const { return isMem; }
@@ -116,7 +116,7 @@ public:
unsigned getLocReg() const { assert(isRegLoc()); return Loc; }
unsigned getLocMemOffset() const { assert(isMemLoc()); return Loc; }
- MVT getLocVT() const { return LocVT; }
+ EVT getLocVT() const { return LocVT; }
LocInfo getLocInfo() const { return HTP; }
bool isExtInLoc() const {
@@ -127,15 +127,15 @@ public:
/// CCAssignFn - This function assigns a location for Val, updating State to
/// reflect the change.
-typedef bool CCAssignFn(unsigned ValNo, MVT ValVT,
- MVT LocVT, CCValAssign::LocInfo LocInfo,
+typedef bool CCAssignFn(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
ISD::ArgFlagsTy ArgFlags, CCState &State);
/// CCCustomFn - This function assigns a location for Val, possibly updating
/// all args to reflect changes and indicates if it handled it. It must set
/// isCustom if it handles the arg and returns true.
-typedef bool CCCustomFn(unsigned &ValNo, MVT &ValVT,
- MVT &LocVT, CCValAssign::LocInfo &LocInfo,
+typedef bool CCCustomFn(unsigned &ValNo, EVT &ValVT,
+ EVT &LocVT, CCValAssign::LocInfo &LocInfo,
ISD::ArgFlagsTy &ArgFlags, CCState &State);
/// CCState - This class holds information needed while lowering arguments and
@@ -189,7 +189,7 @@ public:
/// AnalyzeCallOperands - Same as above except it takes vectors of types
/// and argument flags.
- void AnalyzeCallOperands(SmallVectorImpl<MVT> &ArgVTs,
+ void AnalyzeCallOperands(SmallVectorImpl<EVT> &ArgVTs,
SmallVectorImpl<ISD::ArgFlagsTy> &Flags,
CCAssignFn Fn);
@@ -200,7 +200,7 @@ public:
/// AnalyzeCallResult - Same as above except it's specialized for calls which
/// produce a single value.
- void AnalyzeCallResult(MVT VT, CCAssignFn Fn);
+ void AnalyzeCallResult(EVT VT, CCAssignFn Fn);
/// getFirstUnallocated - Return the first unallocated register in the set, or
/// NumRegs if they are all allocated.
@@ -269,8 +269,8 @@ public:
// HandleByVal - Allocate a stack slot large enough to pass an argument by
// value. The size and alignment information of the argument is encoded in its
// parameter attribute.
- void HandleByVal(unsigned ValNo, MVT ValVT,
- MVT LocVT, CCValAssign::LocInfo LocInfo,
+ void HandleByVal(unsigned ValNo, EVT ValVT,
+ EVT LocVT, CCValAssign::LocInfo LocInfo,
int MinSize, int MinAlign, ISD::ArgFlagsTy ArgFlags);
private:
diff --git a/include/llvm/CodeGen/DAGISelHeader.h b/include/llvm/CodeGen/DAGISelHeader.h
index b2acbc1745..d0a24ebc78 100644
--- a/include/llvm/CodeGen/DAGISelHeader.h
+++ b/include/llvm/CodeGen/DAGISelHeader.h
@@ -35,7 +35,7 @@ static bool IsChainCompatible(SDNode *Chain, SDNode *Op) {
return false;
if (Chain->getNumOperands() > 0) {
SDValue C0 = Chain->getOperand(0);
- if (C0.getValueType() == MVT::Other)
+ if (C0.getValueType() == EVT::Other)
return C0.getNode() != Op && IsChainCompatible(C0.getNode(), Op);
}
return true;
diff --git a/include/llvm/CodeGen/FastISel.h b/include/llvm/CodeGen/FastISel.h
index c7b1a42d06..b159dd970c 100644
--- a/include/llvm/CodeGen/FastISel.h
+++ b/include/llvm/CodeGen/FastISel.h
@@ -137,24 +137,24 @@ protected:
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type and opcode
/// be emitted.
- virtual unsigned FastEmit_(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode);
/// FastEmit_r - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operand be emitted.
///
- virtual unsigned FastEmit_r(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_r(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode, unsigned Op0);
/// FastEmit_rr - This method is called by target-independent code
/// to request that an instruction with the given type, opcode, and
/// register operands be emitted.
///
- virtual unsigned FastEmit_rr(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rr(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1);
@@ -162,8 +162,8 @@ protected:
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_ri(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_ri(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm);
@@ -171,8 +171,8 @@ protected:
/// to request that an instruction with the given type, opcode, and
/// register and floating-point immediate operands be emitted.
///
- virtual unsigned FastEmit_rf(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rf(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
unsigned Op0, ConstantFP *FPImm);
@@ -180,8 +180,8 @@ protected:
/// to request that an instruction with the given type, opcode, and
/// register and immediate operands be emitted.
///
- virtual unsigned FastEmit_rri(MVT::SimpleValueType VT,
- MVT::SimpleValueType RetVT,
+ virtual unsigned FastEmit_rri(EVT::SimpleValueType VT,
+ EVT::SimpleValueType RetVT,
ISD::NodeType Opcode,
unsigned Op0, unsigned Op1, uint64_t Imm);
@@ -189,33 +189,33 @@ protected:
/// to emit an instruction with an immediate operand using FastEmit_ri.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_ri_(MVT::SimpleValueType VT,
+ unsigned FastEmit_ri_(EVT::SimpleValueType VT,
ISD::NodeType Opcode,
unsigned Op0, uint64_t Imm,
- MVT::SimpleValueType ImmType);
+ EVT::SimpleValueType ImmType);
/// FastEmit_rf_ - This method is a wrapper of FastEmit_rf. It first tries
/// to emit an instruction with an immediate operand using FastEmit_rf.
/// If that fails, it materializes the immediate into a register and try
/// FastEmit_rr instead.
- unsigned FastEmit_rf_(M