diff options
| -rw-r--r-- | lib/Target/X86/X86ISelLowering.cpp | 16 | ||||
| -rw-r--r-- | test/CodeGen/X86/avx-shuffle.ll | 10 |
2 files changed, 14 insertions, 12 deletions
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp index 02c9f8ef22..5bd3e2b671 100644 --- a/lib/Target/X86/X86ISelLowering.cpp +++ b/lib/Target/X86/X86ISelLowering.cpp @@ -3757,12 +3757,8 @@ static bool isVPERMILPDMask(const SmallVectorImpl<int> &Mask, EVT VT, if (!Subtarget->hasAVX()) return false; - // Match any permutation of 128-bit vector with 64-bit types - if (NumLanes == 1 && NumElts != 2) - return false; - - // Only match 256-bit with 32 types - if (VT.getSizeInBits() == 256 && NumElts != 4) + // Only match 256-bit with 64-bit types + if (VT.getSizeInBits() != 256 || NumElts != 4) return false; // The mask on the high lane is independent of the low. Both can match @@ -3793,12 +3789,8 @@ static bool isVPERMILPSMask(const SmallVectorImpl<int> &Mask, EVT VT, if (!Subtarget->hasAVX()) return false; - // Match any permutation of 128-bit vector with 32-bit types - if (NumLanes == 1 && NumElts != 4) - return false; - - // Only match 256-bit with 32 types - if (VT.getSizeInBits() == 256 && NumElts != 8) + // Only match 256-bit with 32-bit types + if (VT.getSizeInBits() != 256 || NumElts != 8) return false; // The mask on the high lane should be the same as the low. Actually, diff --git a/test/CodeGen/X86/avx-shuffle.ll b/test/CodeGen/X86/avx-shuffle.ll new file mode 100644 index 0000000000..0db334dd99 --- /dev/null +++ b/test/CodeGen/X86/avx-shuffle.ll @@ -0,0 +1,10 @@ +; RUN: llc < %s -mtriple=x86_64-apple-darwin -mcpu=corei7-avx -mattr=+avx | FileCheck %s + +; PR11102 +define <4 x float> @test1(<4 x float> %a) nounwind { + %b = shufflevector <4 x float> zeroinitializer, <4 x float> %a, <4 x i32> <i32 2, i32 5, i32 undef, i32 undef> + ret <4 x float> %b +; CHECK: test1: +; CHECK: vshufps +; CHECK: vpshufd +} |