diff options
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/IA64/IA64ISelPattern.cpp | 1 | ||||
| -rw-r--r-- | lib/Target/X86/X86ISelPattern.cpp | 1 |
3 files changed, 3 insertions, 0 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index 44a8ef49b7..787edb9189 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -62,6 +62,7 @@ namespace { addRegisterClass(MVT::f64, Alpha::FPRCRegisterClass); addRegisterClass(MVT::f32, Alpha::FPRCRegisterClass); + setOperationAction(ISD::BRCONDTWOWAY, MVT::Other, Expand); setOperationAction(ISD::EXTLOAD , MVT::i1 , Promote); setOperationAction(ISD::EXTLOAD , MVT::f32 , Promote); diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp index 13a4689bd3..07c536adf1 100644 --- a/lib/Target/IA64/IA64ISelPattern.cpp +++ b/lib/Target/IA64/IA64ISelPattern.cpp @@ -55,6 +55,7 @@ namespace { // register class for predicate registers addRegisterClass(MVT::i1, IA64::PRRegisterClass); + setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); setOperationAction(ISD::FP_ROUND_INREG , MVT::f32 , Expand); setSetCCResultType(MVT::i1); diff --git a/lib/Target/X86/X86ISelPattern.cpp b/lib/Target/X86/X86ISelPattern.cpp index 322d129949..61b7e597e1 100644 --- a/lib/Target/X86/X86ISelPattern.cpp +++ b/lib/Target/X86/X86ISelPattern.cpp @@ -56,6 +56,7 @@ namespace { // well. /**/ addRegisterClass(MVT::i1, X86::R8RegisterClass); + setOperationAction(ISD::BRCONDTWOWAY , MVT::Other, Expand); setOperationAction(ISD::MEMMOVE , MVT::Other, Expand); setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16 , Expand); setOperationAction(ISD::ZERO_EXTEND_INREG, MVT::i16 , Expand); |