diff options
| -rw-r--r-- | include/llvm/Target/TargetLowering.h | 5 | ||||
| -rw-r--r-- | test/Analysis/CostModel/X86/testshiftashr.ll | 8 | ||||
| -rw-r--r-- | test/Analysis/CostModel/X86/testshiftlshr.ll | 9 | ||||
| -rw-r--r-- | test/Analysis/CostModel/X86/testshiftshl.ll | 9 |
4 files changed, 17 insertions, 14 deletions
diff --git a/include/llvm/Target/TargetLowering.h b/include/llvm/Target/TargetLowering.h index cb62ed33a1..e169bcf9e4 100644 --- a/include/llvm/Target/TargetLowering.h +++ b/include/llvm/Target/TargetLowering.h @@ -1523,6 +1523,7 @@ public: // or until the element integer type is too big. If a legal type was not // found, fallback to the usual mechanism of widening/splitting the // vector. + EVT OldEltVT = EltVT; while (1) { // Increase the bitwidth of the element to the next pow-of-two // (which is greater than 8 bits). @@ -1541,6 +1542,10 @@ public: return LegalizeKind(TypePromoteInteger, EVT::getVectorVT(Context, EltVT, NumElts)); } + + // Reset the type to the unexpanded type if we did not find a legal vector + // type with a promoted vector element type. + EltVT = OldEltVT; } // Try to widen the vector until a legal type is found. diff --git a/test/Analysis/CostModel/X86/testshiftashr.ll b/test/Analysis/CostModel/X86/testshiftashr.ll index f35eea8716..d96a92fe2a 100644 --- a/test/Analysis/CostModel/X86/testshiftashr.ll +++ b/test/Analysis/CostModel/X86/testshiftashr.ll @@ -113,7 +113,7 @@ entry: define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { entry: ; SSE2: shift32i32 - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 320 {{.*}} ashr ; SSE2-CODEGEN: shift32i32 ; SSE2-CODEGEN: sarl %cl @@ -173,7 +173,7 @@ entry: define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { entry: ; SSE2: shift32i64 - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 320 {{.*}} ashr ; SSE2-CODEGEN: shift32i64 ; SSE2-CODEGEN: sarq %cl @@ -373,7 +373,7 @@ define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { entry: ; SSE2: shift32i32c ; getTypeConversion fails here and promotes this to a i64. - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 8 {{.*}} ashr ; SSE2-CODEGEN: shift32i32c ; SSE2-CODEGEN: psrad $3 %0 = ashr %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, @@ -443,7 +443,7 @@ entry: define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { entry: ; SSE2: shift32i64c - ; SSE2: cost of 256 {{.*}} ashr + ; SSE2: cost of 320 {{.*}} ashr ; SSE2-CODEGEN: shift32i64c ; SSE2-CODEGEN: sarq $3 diff --git a/test/Analysis/CostModel/X86/testshiftlshr.ll b/test/Analysis/CostModel/X86/testshiftlshr.ll index 8d6ef38742..7bc8d89e4a 100644 --- a/test/Analysis/CostModel/X86/testshiftlshr.ll +++ b/test/Analysis/CostModel/X86/testshiftlshr.ll @@ -113,7 +113,7 @@ entry: define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { entry: ; SSE2: shift32i32 - ; SSE2: cost of 256 {{.*}} lshr + ; SSE2: cost of 320 {{.*}} lshr ; SSE2-CODEGEN: shift32i32 ; SSE2-CODEGEN: shrl %cl @@ -173,7 +173,7 @@ entry: define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { entry: ; SSE2: shift32i64 - ; SSE2: cost of 256 {{.*}} lshr + ; SSE2: cost of 320 {{.*}} lshr ; SSE2-CODEGEN: shift32i64 ; SSE2-CODEGEN: shrq %cl @@ -372,8 +372,7 @@ entry: define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { entry: ; SSE2: shift32i32c - ; getTypeConversion fails here and promotes this to a i64. - ; SSE2: cost of 256 {{.*}} lshr + ; SSE2: cost of 8 {{.*}} lshr ; SSE2-CODEGEN: shift32i32c ; SSE2-CODEGEN: psrld $3 %0 = lshr %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, @@ -443,7 +442,7 @@ entry: define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { entry: ; SSE2: shift32i64c - ; SSE2: cost of 256 {{.*}} lshr + ; SSE2: cost of 16 {{.*}} lshr ; SSE2-CODEGEN: shift32i64c ; SSE2-CODEGEN: psrlq $3 diff --git a/test/Analysis/CostModel/X86/testshiftshl.ll b/test/Analysis/CostModel/X86/testshiftshl.ll index f45a698792..40effd0292 100644 --- a/test/Analysis/CostModel/X86/testshiftshl.ll +++ b/test/Analysis/CostModel/X86/testshiftshl.ll @@ -113,7 +113,7 @@ entry: define %shifttype32i32 @shift32i32(%shifttype32i32 %a, %shifttype32i32 %b) { entry: ; SSE2: shift32i32 - ; SSE2: cost of 256 {{.*}} shl + ; SSE2: cost of 80 {{.*}} shl ; SSE2-CODEGEN: shift32i32 ; SSE2-CODEGEN: pmuludq @@ -173,7 +173,7 @@ entry: define %shifttype32i64 @shift32i64(%shifttype32i64 %a, %shifttype32i64 %b) { entry: ; SSE2: shift32i64 - ; SSE2: cost of 256 {{.*}} shl + ; SSE2: cost of 320 {{.*}} shl ; SSE2-CODEGEN: shift32i64 ; SSE2-CODEGEN: shlq %cl @@ -372,8 +372,7 @@ entry: define %shifttypec32i32 @shift32i32c(%shifttypec32i32 %a, %shifttypec32i32 %b) { entry: ; SSE2: shift32i32c - ; getTypeConversion fails here and promotes this to a i64. - ; SSE2: cost of 256 {{.*}} shl + ; SSE2: cost of 8 {{.*}} shl ; SSE2-CODEGEN: shift32i32c ; SSE2-CODEGEN: pslld $3 %0 = shl %shifttypec32i32 %a , <i32 3, i32 3, i32 3, i32 3, @@ -443,7 +442,7 @@ entry: define %shifttypec32i64 @shift32i64c(%shifttypec32i64 %a, %shifttypec32i64 %b) { entry: ; SSE2: shift32i64c - ; SSE2: cost of 256 {{.*}} shl + ; SSE2: cost of 16 {{.*}} shl ; SSE2-CODEGEN: shift32i64c ; SSE2-CODEGEN: psllq $3 |