diff options
| -rw-r--r-- | lib/Target/Mips/MipsISelLowering.cpp | 23 | ||||
| -rw-r--r-- | test/CodeGen/Mips/i64arg.ll | 10 |
2 files changed, 17 insertions, 16 deletions
diff --git a/lib/Target/Mips/MipsISelLowering.cpp b/lib/Target/Mips/MipsISelLowering.cpp index f9401858ce..ea26d57647 100644 --- a/lib/Target/Mips/MipsISelLowering.cpp +++ b/lib/Target/Mips/MipsISelLowering.cpp @@ -1135,17 +1135,6 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, Chain = DAG.getNode(ISD::TokenFactor, dl, MVT::Other, &MemOpChains[0], MemOpChains.size()); - // Build a sequence of copy-to-reg nodes chained together with token - // chain and flag operands which copy the outgoing args into registers. - // The InFlag in necessary since all emitted instructions must be - // stuck together. - SDValue InFlag; - for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { - Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, - RegsToPass[i].second, InFlag); - InFlag = Chain.getValue(1); - } - // If the callee is a GlobalAddress/ExternalSymbol node (quite common, every // direct call is) turn it into a TargetGlobalAddress/TargetExternalSymbol // node so that legalize doesn't hack it. @@ -1172,6 +1161,8 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, LoadSymAddr = true; } + SDValue InFlag; + // Create nodes that load address of callee and copy it to T9 if (IsPIC) { if (LoadSymAddr) { @@ -1197,6 +1188,16 @@ MipsTargetLowering::LowerCall(SDValue Chain, SDValue Callee, Callee = DAG.getRegister(Mips::T9, MVT::i32); } + // Build a sequence of copy-to-reg nodes chained together with token + // chain and flag operands which copy the outgoing args into registers. + // The InFlag in necessary since all emitted instructions must be + // stuck together. + for (unsigned i = 0, e = RegsToPass.size(); i != e; ++i) { + Chain = DAG.getCopyToReg(Chain, dl, RegsToPass[i].first, + RegsToPass[i].second, InFlag); + InFlag = Chain.getValue(1); + } + // MipsJmpLink = #chain, #target_address, #opt_in_flags... // = Chain, Callee, Reg#1, Reg#2, ... // diff --git a/test/CodeGen/Mips/i64arg.ll b/test/CodeGen/Mips/i64arg.ll index 8e8114b27c..560f2e9b08 100644 --- a/test/CodeGen/Mips/i64arg.ll +++ b/test/CodeGen/Mips/i64arg.ll @@ -4,24 +4,24 @@ define void @f1(i64 %ll1, float %f, i64 %ll, i32 %i, float %f2) nounwind { entry: ; CHECK: addu $[[R1:[0-9]+]], $zero, $5 ; CHECK: addu $[[R0:[0-9]+]], $zero, $4 +; CHECK: lw $25, %call16(ff1) ; CHECK: ori $6, ${{[0-9]+}}, 3855 ; CHECK: ori $7, ${{[0-9]+}}, 22136 -; CHECK: lw $25, %call16(ff1) ; CHECK: jalr tail call void @ff1(i32 %i, i64 1085102592623924856) nounwind -; CHECK: lw $[[R2:[0-9]+]], 96($sp) -; CHECK: lw $[[R3:[0-9]+]], 100($sp) +; CHECK: lw $25, %call16(ff2) +; CHECK: lw $[[R2:[0-9]+]], 88($sp) +; CHECK: lw $[[R3:[0-9]+]], 92($sp) ; CHECK: addu $4, $zero, $[[R2]] ; CHECK: addu $5, $zero, $[[R3]] -; CHECK: lw $25, %call16(ff2) ; CHECK: jalr $25 tail call void @ff2(i64 %ll, double 3.000000e+00) nounwind %sub = add nsw i32 %i, -1 ; CHECK: sw $[[R0]], 24($sp) ; CHECK: sw $[[R1]], 28($sp) +; CHECK: lw $25, %call16(ff3) ; CHECK: addu $6, $zero, $[[R2]] ; CHECK: addu $7, $zero, $[[R3]] -; CHECK: lw $25, %call16(ff3) ; CHECK: jalr $25 tail call void @ff3(i32 %i, i64 %ll, i32 %sub, i64 %ll1) nounwind ret void |