diff options
| -rw-r--r-- | lib/Target/IA64/IA64ISelLowering.cpp | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp index 37f15eeb62..d757496f1d 100644 --- a/lib/Target/IA64/IA64ISelLowering.cpp +++ b/lib/Target/IA64/IA64ISelLowering.cpp @@ -192,20 +192,21 @@ IA64TargetLowering::LowerArguments(Function &F, SelectionDAG &DAG) { VirtGPR = MF.getSSARegMap()->createVirtualRegister(getRegClassFor(MVT::i64)); BuildMI(&BB, IA64::PSEUDO_ALLOC, 0, VirtGPR); // we create a PSEUDO_ALLOC (pseudo)instruction for now - +/* BuildMI(&BB, IA64::IDEF, 0, IA64::r1); // hmm: BuildMI(&BB, IA64::IDEF, 0, IA64::r12); BuildMI(&BB, IA64::IDEF, 0, IA64::rp); // ..hmm. - + BuildMI(&BB, IA64::MOV, 1, GP).addReg(IA64::r1); // hmm: BuildMI(&BB, IA64::MOV, 1, SP).addReg(IA64::r12); BuildMI(&BB, IA64::MOV, 1, RP).addReg(IA64::rp); // ..hmm. +*/ unsigned tempOffset=0; |