diff options
| -rw-r--r-- | include/llvm/Target/TargetInstrInfo.h | 11 | ||||
| -rw-r--r-- | lib/CodeGen/InstrSched/InstrScheduling.cpp | 11 | ||||
| -rw-r--r-- | lib/Target/SparcV9/InstrSched/InstrScheduling.cpp | 11 |
3 files changed, 4 insertions, 29 deletions
diff --git a/include/llvm/Target/TargetInstrInfo.h b/include/llvm/Target/TargetInstrInfo.h index 8d15c5df95..f77ba6f25c 100644 --- a/include/llvm/Target/TargetInstrInfo.h +++ b/include/llvm/Target/TargetInstrInfo.h @@ -194,18 +194,11 @@ public: bool isDummyPhiInstr(MachineOpCode opCode) const { return get(opCode).Flags & M_DUMMY_PHI_FLAG; } - // Check if an instruction can be issued before its operands are ready, - // or if a subsequent instruction that uses its result can be issued - // before the results are ready. - // Default to true since most instructions on many architectures allow this. - // - virtual bool hasOperandInterlock(MachineOpCode opCode) const { - return true; - } + virtual bool hasResultInterlock(MachineOpCode opCode) const { return true; } - + // // Latencies for individual instructions and instruction pairs // diff --git a/lib/CodeGen/InstrSched/InstrScheduling.cpp b/lib/CodeGen/InstrSched/InstrScheduling.cpp index 5e66acb060..dd2f45dabd 100644 --- a/lib/CodeGen/InstrSched/InstrScheduling.cpp +++ b/lib/CodeGen/InstrSched/InstrScheduling.cpp @@ -1045,11 +1045,6 @@ NodeCanFillDelaySlot(const SchedulingManager& S, && (*EI)->getDepType() == SchedGraphEdge::CtrlDep) return false; - // for now, don't put an instruction that does not have operand - // interlocks in the delay slot of a branch - if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode())) - return false; - // Finally, if the instruction precedes the branch, we make sure the // instruction can be reordered relative to the branch. We simply check // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. @@ -1326,11 +1321,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S) const SchedGraphNode* dnode = delayNodeVec[i]; if ( ! S.isScheduled(dnode) && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot) - && instrIsFeasible(S, dnode->getOpcode())) - { - assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode()) - && "Instructions without interlocks not yet supported " - "when filling branch delay slots"); + && instrIsFeasible(S, dnode->getOpcode())) { S.scheduleInstr(dnode, nextSlot, nextTime); break; } diff --git a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp index 5e66acb060..dd2f45dabd 100644 --- a/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp +++ b/lib/Target/SparcV9/InstrSched/InstrScheduling.cpp @@ -1045,11 +1045,6 @@ NodeCanFillDelaySlot(const SchedulingManager& S, && (*EI)->getDepType() == SchedGraphEdge::CtrlDep) return false; - // for now, don't put an instruction that does not have operand - // interlocks in the delay slot of a branch - if (! S.getInstrInfo().hasOperandInterlock(node->getOpcode())) - return false; - // Finally, if the instruction precedes the branch, we make sure the // instruction can be reordered relative to the branch. We simply check // if the instr. has only 1 outgoing edge, viz., a CD edge to the branch. @@ -1326,11 +1321,7 @@ DelaySlotInfo::scheduleDelayedNode(SchedulingManager& S) const SchedGraphNode* dnode = delayNodeVec[i]; if ( ! S.isScheduled(dnode) && S.schedInfo.instrCanUseSlot(dnode->getOpcode(), nextSlot) - && instrIsFeasible(S, dnode->getOpcode())) - { - assert(S.getInstrInfo().hasOperandInterlock(dnode->getOpcode()) - && "Instructions without interlocks not yet supported " - "when filling branch delay slots"); + && instrIsFeasible(S, dnode->getOpcode())) { S.scheduleInstr(dnode, nextSlot, nextTime); break; } |