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114 files changed, 0 insertions, 28329 deletions
diff --git a/lib/Target/AMDGPU/AMDGPU.h b/lib/Target/AMDGPU/AMDGPU.h deleted file mode 100644 index 191f495eaa..0000000000 --- a/lib/Target/AMDGPU/AMDGPU.h +++ /dev/null @@ -1,35 +0,0 @@ -//===-- AMDGPU.h - MachineFunction passes hw codegen --------------*- C++ -*-=// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// - -#ifndef AMDGPU_H -#define AMDGPU_H - -#include "AMDGPUTargetMachine.h" -#include "llvm/Support/TargetRegistry.h" -#include "llvm/Target/TargetMachine.h" - -namespace llvm { - -class FunctionPass; -class AMDGPUTargetMachine; - -// R600 Passes -FunctionPass* createR600KernelParametersPass(const TargetData* TD); -FunctionPass *createR600CodeEmitterPass(formatted_raw_ostream &OS); - -// SI Passes -FunctionPass *createSIAssignInterpRegsPass(TargetMachine &tm); -FunctionPass *createSICodeEmitterPass(formatted_raw_ostream &OS); - -// Passes common to R600 and SI -FunctionPass *createAMDGPUConvertToISAPass(TargetMachine &tm); - -} // End namespace llvm - -#endif // AMDGPU_H diff --git a/lib/Target/AMDGPU/AMDGPU.td b/lib/Target/AMDGPU/AMDGPU.td deleted file mode 100644 index 1bb5fb9757..0000000000 --- a/lib/Target/AMDGPU/AMDGPU.td +++ /dev/null @@ -1,21 +0,0 @@ -//===-- AMDIL.td - AMDIL Tablegen files --*- tablegen -*-------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//==-----------------------------------------------------------------------===// - -// Include AMDIL TD files -include "AMDILBase.td" -include "AMDILVersion.td" - -// Include AMDGPU TD files -include "R600Schedule.td" -include "SISchedule.td" -include "Processors.td" -include "AMDGPUInstrInfo.td" -include "AMDGPUIntrinsics.td" -include "AMDGPURegisterInfo.td" -include "AMDGPUInstructions.td" diff --git a/lib/Target/AMDGPU/AMDGPUConvertToISA.cpp b/lib/Target/AMDGPU/AMDGPUConvertToISA.cpp deleted file mode 100644 index 5e8fe9ae21..0000000000 --- a/lib/Target/AMDGPU/AMDGPUConvertToISA.cpp +++ /dev/null @@ -1,63 +0,0 @@ -//===-- AMDGPUConvertToISA.cpp - Lower AMDIL to HW ISA --------------------===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This pass lowers AMDIL machine instructions to the appropriate hardware -// instructions. -// -//===----------------------------------------------------------------------===// - -#include "AMDGPU.h" -#include "AMDGPUInstrInfo.h" -#include "llvm/CodeGen/MachineFunctionPass.h" - -#include <stdio.h> -using namespace llvm; - -namespace { - -class AMDGPUConvertToISAPass : public MachineFunctionPass { - -private: - static char ID; - TargetMachine &TM; - -public: - AMDGPUConvertToISAPass(TargetMachine &tm) : - MachineFunctionPass(ID), TM(tm) { } - - virtual bool runOnMachineFunction(MachineFunction &MF); - - virtual const char *getPassName() const {return "AMDGPU Convert to ISA";} - -}; - -} // End anonymous namespace - -char AMDGPUConvertToISAPass::ID = 0; - -FunctionPass *llvm::createAMDGPUConvertToISAPass(TargetMachine &tm) { - return new AMDGPUConvertToISAPass(tm); -} - -bool AMDGPUConvertToISAPass::runOnMachineFunction(MachineFunction &MF) -{ - const AMDGPUInstrInfo * TII = - static_cast<const AMDGPUInstrInfo*>(TM.getInstrInfo()); - - for (MachineFunction::iterator BB = MF.begin(), BB_E = MF.end(); - BB != BB_E; ++BB) { - MachineBasicBlock &MBB = *BB; - for (MachineBasicBlock::iterator I = MBB.begin(), E = MBB.end(); - I != E; ++I) { - MachineInstr &MI = *I; - TII->convertToISA(MI, MF, MBB.findDebugLoc(I)); - } - } - return false; -} diff --git a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp b/lib/Target/AMDGPU/AMDGPUISelLowering.cpp deleted file mode 100644 index b3d27f762e..0000000000 --- a/lib/Target/AMDGPU/AMDGPUISelLowering.cpp +++ /dev/null @@ -1,393 +0,0 @@ -//===-- AMDGPUISelLowering.cpp - AMDGPU Common DAG lowering functions -----===// -// -// The LLVM Compiler Infrastructure -// -// This file is distributed under the University of Illinois Open Source -// License. See LICENSE.TXT for details. -// -//===----------------------------------------------------------------------===// -// -// This is the parent TargetLowering class for hardware code gen targets. -// -//===----------------------------------------------------------------------===// - -#include "AMDGPUISelLowering.h" -#include "AMDILIntrinsicInfo.h" -#include "AMDGPUUtil.h" -#include "llvm/CodeGen/MachineRegisterInfo.h" - -using namespace llvm; - -AMDGPUTargetLowering::AMDGPUTargetLowering(TargetMachine &TM) : - AMDILTargetLowering(TM) -{ - // We need to custom lower some of the intrinsics - setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); - - setOperationAction(ISD::SELECT_CC, MVT::f32, Custom); - setOperationAction(ISD::SELECT_CC, MVT::i32, Custom); - - // Library functions. These default to Expand, but we have instructions - // for them. - setOperationAction(ISD::FCEIL, MVT::f32, Legal); - setOperationAction(ISD::FEXP2, MVT::f32, Legal); - setOperationAction(ISD::FRINT, MVT::f32, Legal); - - setOperationAction(ISD::UDIV, MVT::i32, Expand); - setOperationAction(ISD::UDIVREM, MVT::i32, Custom); - setOperationAction(ISD::UREM, MVT::i32, Expand); -} - -SDValue AMDGPUTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) - const -{ - switch (Op.getOpcode()) { - default: return AMDILTargetLowering::LowerOperation(Op, DAG); - case ISD::INTRINSIC_WO_CHAIN: return LowerINTRINSIC_WO_CHAIN(Op, DAG); - case ISD::SELECT_CC: return LowerSELECT_CC(Op, DAG); - case ISD::UDIVREM: return LowerUDIVREM(Op, DAG); - } -} - -SDValue AMDGPUTargetLowering::LowerINTRINSIC_WO_CHAIN(SDVa |