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-rw-r--r--include/llvm/CodeGen/DwarfWriter.h5
-rw-r--r--include/llvm/CodeGen/MachineDebugInfo.h7
-rw-r--r--include/llvm/CodeGen/SelectionDAGNodes.h13
-rw-r--r--lib/CodeGen/SelectionDAG/DAGCombiner.cpp3
-rw-r--r--lib/CodeGen/SelectionDAG/LegalizeDAG.cpp84
-rw-r--r--lib/CodeGen/SelectionDAG/SelectionDAG.cpp1
-rw-r--r--lib/Target/Alpha/AlphaISelLowering.cpp1
-rw-r--r--lib/Target/IA64/IA64ISelLowering.cpp1
-rw-r--r--lib/Target/IA64/IA64ISelPattern.cpp1
-rw-r--r--lib/Target/PowerPC/PPCAsmPrinter.cpp6
-rw-r--r--lib/Target/PowerPC/PPCISelLowering.cpp5
-rw-r--r--lib/Target/PowerPC/PPCInstrInfo.td11
-rw-r--r--lib/Target/Sparc/SparcISelDAGToDAG.cpp1
-rw-r--r--lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp1
-rw-r--r--lib/Target/TargetSelectionDAG.td9
-rw-r--r--lib/Target/X86/X86ISelLowering.cpp1
16 files changed, 98 insertions, 52 deletions
diff --git a/include/llvm/CodeGen/DwarfWriter.h b/include/llvm/CodeGen/DwarfWriter.h
index 11e5623b0d..1a7c5a5666 100644
--- a/include/llvm/CodeGen/DwarfWriter.h
+++ b/include/llvm/CodeGen/DwarfWriter.h
@@ -550,8 +550,9 @@ namespace llvm {
///
void EmitInitial() const;
- /// ShouldEmitDwarf - Determine if dwarf declarations should be made.
- ///
+ /// ShouldEmitDwarf - Returns true if dwarf declarations should be made.
+ /// When called it also checks to see if debug info is newly available. if
+ /// so the initial dwarf headers are emitted.
bool ShouldEmitDwarf();
/// BeginModule - Emit all dwarf sections that should come prior to the
diff --git a/include/llvm/CodeGen/MachineDebugInfo.h b/include/llvm/CodeGen/MachineDebugInfo.h
index c728418a89..039bdbc0d5 100644
--- a/include/llvm/CodeGen/MachineDebugInfo.h
+++ b/include/llvm/CodeGen/MachineDebugInfo.h
@@ -52,6 +52,13 @@ public:
///
unsigned getNextUniqueID() { return UniqueID++; }
+ /// RecordLabel - Records location information and associates it with a
+ /// debug label. Returns unique label id.
+ unsigned RecordLabel(unsigned Line, unsigned Col, unsigned SrcFile) {
+ // FIXME - actually record.
+ return getNextUniqueID();
+ }
+
bool doInitialization();
bool doFinalization();
diff --git a/include/llvm/CodeGen/SelectionDAGNodes.h b/include/llvm/CodeGen/SelectionDAGNodes.h
index 800ad3932b..124da2e6cd 100644
--- a/include/llvm/CodeGen/SelectionDAGNodes.h
+++ b/include/llvm/CodeGen/SelectionDAGNodes.h
@@ -355,12 +355,17 @@ namespace ISD {
LOCATION,
// DEBUG_LOC - This node is used to represent source line information
- // embedded in the code. It takes token chain as input, then a line number,
- // then a column then a file id (provided by MachineDebugInfo), then a
- // unique id (provided by MachineDebugInfo for label gen). It produces a
- // token chain as output.
+ // embedded in the code. It takes a token chain as input, then a line
+ // number, then a column then a file id (provided by MachineDebugInfo.) It
+ // produces a token chain as output.
DEBUG_LOC,
+ // DEBUG_LABEL - This node is used to mark a location in the code where a
+ // label should be generated for use by the debug information. It takes a
+ // token chain as input, the a unique id (provided by MachineDebugInfo.) It
+ // produces a token chain as output.
+ DEBUG_LABEL,
+
// BUILTIN_OP_END - This must be the last enum value in this list.
BUILTIN_OP_END,
};
diff --git a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
index 1cfa305d85..30a4c9f637 100644
--- a/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
+++ b/lib/CodeGen/SelectionDAG/DAGCombiner.cpp
@@ -2117,8 +2117,7 @@ SDOperand DAGCombiner::visitDEBUGLOC(SDNode *N) {
return DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Chain.getOperand(0),
N->getOperand(1),
N->getOperand(2),
- N->getOperand(3),
- N->getOperand(4));
+ N->getOperand(3));
}
return SDOperand();
diff --git a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
index dec782a070..3e470f25b6 100644
--- a/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/LegalizeDAG.cpp
@@ -619,20 +619,33 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
default: assert(0 && "This action is not supported yet!");
case TargetLowering::Expand: {
MachineDebugInfo *DebugInfo = DAG.getMachineDebugInfo();
- if (TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other) && DebugInfo) {
- std::vector<SDOperand> Ops;
- Ops.push_back(Tmp1); // chain
- Ops.push_back(Node->getOperand(1)); // line #
- Ops.push_back(Node->getOperand(2)); // col #
- const std::string &fname =
+ bool useDEBUG_LOC = TLI.isOperationLegal(ISD::DEBUG_LOC, MVT::Other);
+ bool useDEBUG_LABEL = TLI.isOperationLegal(ISD::DEBUG_LABEL, MVT::Other);
+
+ if (DebugInfo && (useDEBUG_LOC || useDEBUG_LABEL)) {
+ const std::string &FName =
cast<StringSDNode>(Node->getOperand(3))->getValue();
- const std::string &dirname =
+ const std::string &DirName =
cast<StringSDNode>(Node->getOperand(4))->getValue();
- unsigned srcfile = DebugInfo->getUniqueSourceID(fname, dirname);
- Ops.push_back(DAG.getConstant(srcfile, MVT::i32)); // source file id
- unsigned id = DebugInfo->getNextUniqueID();
- Ops.push_back(DAG.getConstant(id, MVT::i32)); // label id
- Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
+ unsigned SrcFile = DebugInfo->getUniqueSourceID(FName, DirName);
+
+ std::vector<SDOperand> Ops;
+ Ops.push_back(Tmp1); // chain
+ SDOperand LineOp = Node->getOperand(1);
+ SDOperand ColOp = Node->getOperand(2);
+
+ if (useDEBUG_LOC) {
+ Ops.push_back(LineOp); // line #
+ Ops.push_back(ColOp); // col #
+ Ops.push_back(DAG.getConstant(SrcFile, MVT::i32)); // source file id
+ Result = DAG.getNode(ISD::DEBUG_LOC, MVT::Other, Ops);
+ } else {
+ unsigned Line = dyn_cast<ConstantSDNode>(LineOp)->getValue();
+ unsigned Col = dyn_cast<ConstantSDNode>(ColOp)->getValue();
+ unsigned ID = DebugInfo->RecordLabel(Line, Col, SrcFile);
+ Ops.push_back(DAG.getConstant(ID, MVT::i32));
+ Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Ops);
+ }
} else {
Result = Tmp1; // chain
}
@@ -661,27 +674,40 @@ SDOperand SelectionDAGLegalize::LegalizeOp(SDOperand Op) {
break;
case ISD::DEBUG_LOC:
- assert(Node->getNumOperands() == 5 && "Invalid DEBUG_LOC node!");
+ assert(Node->getNumOperands() == 4 && "Invalid DEBUG_LOC node!");
switch (TLI.getOperationAction(ISD::DEBUG_LOC, MVT::Other)) {
case TargetLowering::Promote:
case TargetLowering::Expand:
default: assert(0 && "This action is not supported yet!");
- case TargetLowering::Legal: {
- SDOperand Tmp5;
- Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
- Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
- Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
- Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
- Tmp5 = LegalizeOp(Node->getOperand(4)); // Legalize the label id.
-
- if (Tmp1 != Node->getOperand(0) ||
- Tmp2 != Node->getOperand(1) ||
- Tmp3 != Node->getOperand(2) ||
- Tmp4 != Node->getOperand(3) ||
- Tmp5 != Node->getOperand(4)) {
- Result =
- DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4, Tmp5);
- }
+ case TargetLowering::Legal:
+ Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
+ Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the line #.
+ Tmp3 = LegalizeOp(Node->getOperand(2)); // Legalize the col #.
+ Tmp4 = LegalizeOp(Node->getOperand(3)); // Legalize the source file id.
+
+ if (Tmp1 != Node->getOperand(0) ||
+ Tmp2 != Node->getOperand(1) ||
+ Tmp3 != Node->getOperand(2) ||
+ Tmp4 != Node->getOperand(3)) {
+ Result = DAG.getNode(ISD::DEBUG_LOC,MVT::Other, Tmp1, Tmp2, Tmp3, Tmp4);
+ }
+ break;
+ }
+ break;
+
+ case ISD::DEBUG_LABEL:
+ assert(Node->getNumOperands() == 2 && "Invalid DEBUG_LABEL node!");
+ switch (TLI.getOperationAction(ISD::DEBUG_LABEL, MVT::Other)) {
+ case TargetLowering::Promote:
+ case TargetLowering::Expand:
+ default: assert(0 && "This action is not supported yet!");
+ case TargetLowering::Legal:
+ Tmp1 = LegalizeOp(Node->getOperand(0)); // Legalize the chain.
+ Tmp2 = LegalizeOp(Node->getOperand(1)); // Legalize the label id.
+
+ if (Tmp1 != Node->getOperand(0) ||
+ Tmp2 != Node->getOperand(1)) {
+ Result = DAG.getNode(ISD::DEBUG_LABEL, MVT::Other, Tmp1, Tmp2);
}
break;
}
diff --git a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
index 853b48c9c8..b067c122ac 100644
--- a/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
+++ b/lib/CodeGen/SelectionDAG/SelectionDAG.cpp
@@ -2005,6 +2005,7 @@ const char *SDNode::getOperationName(const SelectionDAG *G) const {
// Debug info
case ISD::LOCATION: return "location";
case ISD::DEBUG_LOC: return "debug_loc";
+ case ISD::DEBUG_LABEL: return "debug_label";
case ISD::CONDCODE:
switch (cast<CondCodeSDNode>(this)->get()) {
diff --git a/lib/Target/Alpha/AlphaISelLowering.cpp b/lib/Target/Alpha/AlphaISelLowering.cpp
index cc4144c0b2..9ce9a3ebe0 100644
--- a/lib/Target/Alpha/AlphaISelLowering.cpp
+++ b/lib/Target/Alpha/AlphaISelLowering.cpp
@@ -103,7 +103,6 @@ AlphaTargetLowering::AlphaTargetLowering(TargetMachine &TM) : TargetLowering(TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool and
// ExternalSymbols nodes into the appropriate instructions to
diff --git a/lib/Target/IA64/IA64ISelLowering.cpp b/lib/Target/IA64/IA64ISelLowering.cpp
index d63157fb44..fb3b20476c 100644
--- a/lib/Target/IA64/IA64ISelLowering.cpp
+++ b/lib/Target/IA64/IA64ISelLowering.cpp
@@ -74,7 +74,6 @@ IA64TargetLowering::IA64TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
//IA64 has these, but they are not implemented
setOperationAction(ISD::CTTZ , MVT::i64 , Expand);
diff --git a/lib/Target/IA64/IA64ISelPattern.cpp b/lib/Target/IA64/IA64ISelPattern.cpp
index a98c275a92..31e225913d 100644
--- a/lib/Target/IA64/IA64ISelPattern.cpp
+++ b/lib/Target/IA64/IA64ISelPattern.cpp
@@ -102,7 +102,6 @@ namespace {
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
diff --git a/lib/Target/PowerPC/PPCAsmPrinter.cpp b/lib/Target/PowerPC/PPCAsmPrinter.cpp
index abbe95a852..de865db69b 100644
--- a/lib/Target/PowerPC/PPCAsmPrinter.cpp
+++ b/lib/Target/PowerPC/PPCAsmPrinter.cpp
@@ -252,7 +252,9 @@ namespace {
bool doFinalization(Module &M);
void getAnalysisUsage(AnalysisUsage &AU) const {
+ AU.setPreservesAll();
AU.addRequired<MachineDebugInfo>();
+ PPCAsmPrinter::getAnalysisUsage(AU);
}
};
@@ -418,6 +420,9 @@ void PPCAsmPrinter::printMachineInstruction(const MachineInstr *MI) {
/// method to print assembly for each instruction.
///
bool DarwinAsmPrinter::runOnMachineFunction(MachineFunction &MF) {
+ // FIXME - is this the earliest this can be set.
+ DW.SetDebugInfo(&getAnalysis<MachineDebugInfo>());
+
SetupMachineFunction(MF);
O << "\n\n";
@@ -486,7 +491,6 @@ bool DarwinAsmPrinter::doInitialization(Module &M) {
Mang->setUseQuotes(true);
// Emit initial debug information.
- DW.SetDebugInfo(getAnalysisToUpdate<MachineDebugInfo>());
DW.BeginModule();
return false;
}
diff --git a/lib/Target/PowerPC/PPCISelLowering.cpp b/lib/Target/PowerPC/PPCISelLowering.cpp
index 01d8f075b7..8eb4ac303a 100644
--- a/lib/Target/PowerPC/PPCISelLowering.cpp
+++ b/lib/Target/PowerPC/PPCISelLowering.cpp
@@ -94,8 +94,11 @@ PPCTargetLowering::PPCTargetLowering(TargetMachine &TM)
// PowerPC does not have truncstore for i1.
setOperationAction(ISD::TRUNCSTORE, MVT::i1, Promote);
- // PowerPC doesn't have line number support yet.
+ // Support label based line numbers.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
+ // FIXME - use subtarget debug flags
+ if (TM.getSubtarget<PPCSubtarget>().isDarwin())
+ setOperationAction(ISD::DEBUG_LABEL, MVT::Other, Expand);
// We want to legalize GlobalAddress and ConstantPool nodes into the
// appropriate instructions to materialize the address.
diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td
index 3d3424d17b..66b1bad4b0 100644
--- a/lib/Target/PowerPC/PPCInstrInfo.td
+++ b/lib/Target/PowerPC/PPCInstrInfo.td
@@ -955,11 +955,14 @@ def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD),
// DWARF Pseudo Instructions
//
-def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file,
- i32imm:$id),
- "; .loc $file, $line, $col\nLdebug_loc$id:",
+def DWARF_LOC : Pseudo<(ops i32imm:$line, i32imm:$col, i32imm:$file),
+ "; .loc $file, $line, $col",
[(dwarf_loc (i32 imm:$line), (i32 imm:$col),
- (i32 imm:$file), (i32 imm:$id))]>;
+ (i32 imm:$file))]>;
+
+def DWARF_LABEL : Pseudo<(ops i32imm:$id),
+ "\nLdebug_loc$id:",
+ [(dwarf_label (i32 imm:$id))]>;
//===----------------------------------------------------------------------===//
// PowerPC Instruction Patterns
diff --git a/lib/Target/Sparc/SparcISelDAGToDAG.cpp b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
index 6c93a26f24..b80430dba5 100644
--- a/lib/Target/Sparc/SparcISelDAGToDAG.cpp
+++ b/lib/Target/Sparc/SparcISelDAGToDAG.cpp
@@ -153,7 +153,6 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
}
diff --git a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
index 6c93a26f24..b80430dba5 100644
--- a/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
+++ b/lib/Target/SparcV8/SparcV8ISelDAGToDAG.cpp
@@ -153,7 +153,6 @@ SparcV8TargetLowering::SparcV8TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
computeRegisterProperties();
}
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td
index 13cd40e391..9b19adac3b 100644
--- a/lib/Target/TargetSelectionDAG.td
+++ b/lib/Target/TargetSelectionDAG.td
@@ -440,9 +440,12 @@ class ComplexPattern<ValueType ty, int numops, string fn, list<SDNode> roots = [
//===----------------------------------------------------------------------===//
// Dwarf support.
//
-def SDT_dwarf_loc : SDTypeProfile<0, 4,
- [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>, SDTCisInt<3>]>;
-def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
+def SDT_dwarf_loc : SDTypeProfile<0, 3,
+ [SDTCisInt<0>, SDTCisInt<1>, SDTCisInt<2>]>;
+def dwarf_loc : SDNode<"ISD::DEBUG_LOC", SDT_dwarf_loc,[SDNPHasChain]>;
+
+def SDT_dwarf_label : SDTypeProfile<0, 1, [SDTCisInt<0>]>;
+def dwarf_label : SDNode<"ISD::DEBUG_LABEL", SDT_dwarf_label,[SDNPHasChain]>;
diff --git a/lib/Target/X86/X86ISelLowering.cpp b/lib/Target/X86/X86ISelLowering.cpp
index 1811f62b0b..304165e4a8 100644
--- a/lib/Target/X86/X86ISelLowering.cpp
+++ b/lib/Target/X86/X86ISelLowering.cpp
@@ -130,7 +130,6 @@ X86TargetLowering::X86TargetLowering(TargetMachine &TM)
// We don't have line number support yet.
setOperationAction(ISD::LOCATION, MVT::Other, Expand);
- setOperationAction(ISD::DEBUG_LOC, MVT::Other, Expand);
if (X86ScalarSSE) {
// Set up the FP register classes.
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-07-09 23:05:01 +0000