diff options
| -rw-r--r-- | include/llvm/CodeGen/ScheduleDAG.h | 2 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp | 8 |
2 files changed, 6 insertions, 4 deletions
diff --git a/include/llvm/CodeGen/ScheduleDAG.h b/include/llvm/CodeGen/ScheduleDAG.h index 69aec43920..b3d05c700a 100644 --- a/include/llvm/CodeGen/ScheduleDAG.h +++ b/include/llvm/CodeGen/ScheduleDAG.h @@ -328,7 +328,7 @@ namespace llvm { /// isInstr - Return true if this SUnit refers to a machine instruction as /// opposed to an SDNode. - bool isInstr() const { return !Node; } + bool isInstr() const { return Instr; } /// setInstr - Assign the instruction for the SUnit. /// This may be used during post-regalloc scheduling. diff --git a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp index d6368047bc..a51595f1b0 100644 --- a/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp +++ b/lib/CodeGen/SelectionDAG/ScheduleDAGRRList.cpp @@ -348,7 +348,10 @@ void ScheduleDAGRRList::ReleasePredecessors(SUnit *SU) { /// Check to see if any of the pending instructions are ready to issue. If /// so, add them to the available queue. void ScheduleDAGRRList::ReleasePending() { - assert(!EnableSchedCycles && "requires --enable-sched-cycles" ); + if (!EnableSchedCycles) { + assert(PendingQueue.empty() && "pending instrs not allowed in this mode"); + return; + } // If the available queue is empty, it is safe to reset MinAvailableCycle. if (AvailableQueue->empty()) @@ -634,8 +637,7 @@ void ScheduleDAGRRList::BacktrackBottomUp(SUnit *SU, SUnit *BtSU) { RestoreHazardCheckerBottomUp(); - if (EnableSchedCycles) - ReleasePending(); + ReleasePending(); ++NumBacktracks; } |