diff options
| -rw-r--r-- | lib/Target/TargetSelectionDAG.td | 2 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrMMX.td | 18 | ||||
| -rw-r--r-- | lib/Target/X86/X86InstrSSE.td | 36 |
3 files changed, 56 insertions, 0 deletions
diff --git a/lib/Target/TargetSelectionDAG.td b/lib/Target/TargetSelectionDAG.td index c3237399a0..94efe42e41 100644 --- a/lib/Target/TargetSelectionDAG.td +++ b/lib/Target/TargetSelectionDAG.td @@ -308,6 +308,8 @@ def truncst : SDNode<"ISD::TRUNCSTORE" , SDTTruncStore, [SDNPHasChain]>; def vector_shuffle : SDNode<"ISD::VECTOR_SHUFFLE", SDTVecShuffle, []>; def build_vector : SDNode<"ISD::BUILD_VECTOR", SDTypeProfile<1, 0, []>, []>; +def scalar_to_vector : SDNode<"ISD::SCALAR_TO_VECTOR", SDTypeProfile<1, 1, []>, + []>; //===----------------------------------------------------------------------===// // Selection DAG Condition Codes diff --git a/lib/Target/X86/X86InstrMMX.td b/lib/Target/X86/X86InstrMMX.td index e1cca71a98..4152340225 100644 --- a/lib/Target/X86/X86InstrMMX.td +++ b/lib/Target/X86/X86InstrMMX.td @@ -22,6 +22,24 @@ def IMPLICIT_DEF_VR64 : I<0, Pseudo, (ops VR64:$dst), def : Pat<(v4i16 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; def : Pat<(v2i32 (undef)), (IMPLICIT_DEF_VR64)>, Requires<[HasMMX]>; +def SCALAR_TO_VECTOR_V8I8 : I<0, Pseudo, (ops VR64:$dst, R8:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR64:$dst, + (v8i8 (scalar_to_vector R8:$src)))]>, + Requires<[HasMMX]>; + +def SCALAR_TO_VECTOR_V4I16 : I<0, Pseudo, (ops VR64:$dst, R16:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR64:$dst, + (v4i16 (scalar_to_vector R16:$src)))]>, + Requires<[HasMMX]>; + +def SCALAR_TO_VECTOR_V2I32 : I<0, Pseudo, (ops VR64:$dst, R32:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR64:$dst, + (v2i32 (scalar_to_vector R32:$src)))]>, + Requires<[HasMMX]>; + // Move Instructions def MOVD64rr : I<0x6E, MRMSrcReg, (ops VR64:$dst, R32:$src), "movd {$src, $dst|$dst, $src}", []>, TB, diff --git a/lib/Target/X86/X86InstrSSE.td b/lib/Target/X86/X86InstrSSE.td index 92412cfd63..f8efb5101e 100644 --- a/lib/Target/X86/X86InstrSSE.td +++ b/lib/Target/X86/X86InstrSSE.td @@ -353,6 +353,42 @@ def : Pat<(v8i16 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; def : Pat<(v4i32 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; def : Pat<(v2i64 (undef)), (IMPLICIT_DEF_VR128)>, Requires<[HasSSE2]>; +def SCALAR_TO_VECTOR_V4F32 : I<0, Pseudo, (ops VR128:$dst, FR32:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v4f32 (scalar_to_vector FR32:$src)))]>, + Requires<[HasSSE1]>; + +def SCALAR_TO_VECTOR_V2F64 : I<0, Pseudo, (ops VR128:$dst, FR64:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v2f64 (scalar_to_vector FR64:$src)))]>, + Requires<[HasSSE2]>; + +def SCALAR_TO_VECTOR_V16I8 : I<0, Pseudo, (ops VR128:$dst, R8:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v16i8 (scalar_to_vector R8:$src)))]>, + Requires<[HasSSE2]>; + +def SCALAR_TO_VECTOR_V8I16 : I<0, Pseudo, (ops VR128:$dst, R16:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v8i16 (scalar_to_vector R16:$src)))]>, + Requires<[HasSSE2]>; + +def SCALAR_TO_VECTOR_V4I32 : I<0, Pseudo, (ops VR128:$dst, R32:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v4i32 (scalar_to_vector R32:$src)))]>, + Requires<[HasSSE2]>; + +def SCALAR_TO_VECTOR_V2I64 : I<0, Pseudo, (ops VR128:$dst, VR64:$src), + "#SCALAR_TO_VECTOR $src", + [(set VR128:$dst, + (v2i64 (scalar_to_vector VR64:$src)))]>, + Requires<[HasSSE2]>; + // Move Instructions def MOVAPSrr : PSI<0x28, MRMSrcReg, (ops VR128:$dst, VR128:$src), "movaps {$src, $dst|$dst, $src}", []>; |