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-rw-r--r--lib/CodeGen/LiveVariables.cpp34
-rw-r--r--lib/CodeGen/PrologEpilogInserter.cpp9
-rw-r--r--lib/CodeGen/RegAllocLocal.cpp43
-rw-r--r--lib/CodeGen/RegAllocSimple.cpp12
-rw-r--r--utils/TableGen/InstrInfoEmitter.cpp8
-rw-r--r--utils/TableGen/RegisterInfoEmitter.cpp6
6 files changed, 64 insertions, 48 deletions
diff --git a/lib/CodeGen/LiveVariables.cpp b/lib/CodeGen/LiveVariables.cpp
index d38ed274e3..2a9b70d3b0 100644
--- a/lib/CodeGen/LiveVariables.cpp
+++ b/lib/CodeGen/LiveVariables.cpp
@@ -108,12 +108,14 @@ void LiveVariables::HandlePhysRegUse(unsigned Reg, MachineInstr *MI) {
if (PhysRegInfo[Reg]) {
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = true;
- } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
- for (; unsigned NReg = AliasSet[0]; ++AliasSet)
- if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
- PhysRegInfo[NReg] = MI;
- PhysRegUsed[NReg] = true;
+ } else {
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+ *AliasSet; ++AliasSet) {
+ if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) {
+ PhysRegInfo[*AliasSet] = MI;
+ PhysRegUsed[*AliasSet] = true;
}
+ }
}
}
@@ -124,15 +126,17 @@ void LiveVariables::HandlePhysRegDef(unsigned Reg, MachineInstr *MI) {
RegistersKilled.insert(std::make_pair(LastUse, Reg));
else
RegistersDead.insert(std::make_pair(LastUse, Reg));
- } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg)) {
- for (; unsigned NReg = AliasSet[0]; ++AliasSet)
- if (MachineInstr *LastUse = PhysRegInfo[NReg]) {
- if (PhysRegUsed[NReg])
- RegistersKilled.insert(std::make_pair(LastUse, NReg));
+ } else {
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+ *AliasSet; ++AliasSet) {
+ if (MachineInstr *LastUse = PhysRegInfo[*AliasSet]) {
+ if (PhysRegUsed[*AliasSet])
+ RegistersKilled.insert(std::make_pair(LastUse, *AliasSet));
else
- RegistersDead.insert(std::make_pair(LastUse, NReg));
- PhysRegInfo[NReg] = 0; // Kill the aliased register
+ RegistersDead.insert(std::make_pair(LastUse, *AliasSet));
+ PhysRegInfo[*AliasSet] = 0; // Kill the aliased register
}
+ }
}
PhysRegInfo[Reg] = MI;
PhysRegUsed[Reg] = false;
@@ -206,9 +210,9 @@ bool LiveVariables::runOnMachineFunction(MachineFunction &MF) {
NumOperandsToProcess = 1;
// Loop over implicit uses, using them.
- if (const unsigned *ImplicitUses = MID.ImplicitUses)
- for (unsigned i = 0; ImplicitUses[i]; ++i)
- HandlePhysRegUse(ImplicitUses[i], MI);
+ for (const unsigned *ImplicitUses = MID.ImplicitUses;
+ *ImplicitUses; ++ImplicitUses)
+ HandlePhysRegUse(*ImplicitUses, MI);
// Process all explicit uses...
for (unsigned i = 0; i != NumOperandsToProcess; ++i) {
diff --git a/lib/CodeGen/PrologEpilogInserter.cpp b/lib/CodeGen/PrologEpilogInserter.cpp
index 13cd353362..0ceb866965 100644
--- a/lib/CodeGen/PrologEpilogInserter.cpp
+++ b/lib/CodeGen/PrologEpilogInserter.cpp
@@ -127,12 +127,15 @@ void PEI::saveCallerSavedRegisters(MachineFunction &Fn) {
unsigned Reg = CSRegs[i];
if (ModifiedRegs[Reg]) {
RegsToSave.push_back(Reg); // If modified register...
- } else if (const unsigned *AliasSet = RegInfo->getAliasSet(Reg))
- for (unsigned j = 0; AliasSet[j]; ++j) // Check alias registers too...
- if (ModifiedRegs[AliasSet[j]]) {
+ } else {
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(Reg);
+ *AliasSet; ++AliasSet) { // Check alias registers too...
+ if (ModifiedRegs[*AliasSet]) {
RegsToSave.push_back(Reg);
break;
}
+ }
+ }
}
if (RegsToSave.empty())
diff --git a/lib/CodeGen/RegAllocLocal.cpp b/lib/CodeGen/RegAllocLocal.cpp
index 331a291753..6b71e288e7 100644
--- a/lib/CodeGen/RegAllocLocal.cpp
+++ b/lib/CodeGen/RegAllocLocal.cpp
@@ -120,9 +120,10 @@ namespace {
///
bool areRegsEqual(unsigned R1, unsigned R2) const {
if (R1 == R2) return true;
- if (const unsigned *AliasSet = RegInfo->getAliasSet(R2))
- for (unsigned i = 0; AliasSet[i]; ++i)
- if (AliasSet[i] == R1) return true;
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(R2);
+ *AliasSet; ++AliasSet) {
+ if (*AliasSet == R1) return true;
+ }
return false;
}
@@ -271,14 +272,15 @@ void RA::spillPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
if (PI != PhysRegsUsed.end()) { // Only spill it if it's used!
if (PI->second || !OnlyVirtRegs)
spillVirtReg(MBB, I, PI->second, PhysReg);
- } else if (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg)) {
+ } else {
// If the selected register aliases any other registers, we must make
// sure that one of the aliases isn't alive...
- for (unsigned i = 0; AliasSet[i]; ++i) {
- PI = PhysRegsUsed.find(AliasSet[i]);
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
+ *AliasSet; ++AliasSet) {
+ PI = PhysRegsUsed.find(*AliasSet);
if (PI != PhysRegsUsed.end()) // Spill aliased register...
if (PI->second || !OnlyVirtRegs)
- spillVirtReg(MBB, I, PI->second, AliasSet[i]);
+ spillVirtReg(MBB, I, PI->second, *AliasSet);
}
}
}
@@ -308,10 +310,10 @@ bool RA::isPhysRegAvailable(unsigned PhysReg) const {
// If the selected register aliases any other allocated registers, it is
// not free!
- if (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg))
- for (unsigned i = 0; AliasSet[i]; ++i)
- if (PhysRegsUsed.count(AliasSet[i])) // Aliased register in use?
- return false; // Can't use this reg then.
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(PhysReg);
+ *AliasSet; ++AliasSet)
+ if (PhysRegsUsed.count(*AliasSet)) // Aliased register in use?
+ return false; // Can't use this reg then.
return true;
}
@@ -414,12 +416,13 @@ unsigned RA::getReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator &I,
} else {
// If one of the registers aliased to the current register is
// compatible, use it.
- if (const unsigned *AliasSet = RegInfo->getAliasSet(R))
- for (unsigned a = 0; AliasSet[a]; ++a)
- if (RegInfo->getRegClass(AliasSet[a]) == RC) {
- PhysReg = AliasSet[a]; // Take an aliased register
- break;
- }
+ for (const unsigned *AliasSet = RegInfo->getAliasSet(R);
+ *AliasSet; ++AliasSet) {
+ if (RegInfo->getRegClass(*AliasSet) == RC) {
+ PhysReg = *AliasSet; // Take an aliased register
+ break;
+ }
+ }
}
}
}
@@ -485,9 +488,9 @@ void RA::AllocateBasicBlock(MachineBasicBlock &MBB) {
// Loop over the implicit uses, making sure that they are at the head of the
// use order list, so they don't get reallocated.
- if (const unsigned *ImplicitUses = TID.ImplicitUses)
- for (unsigned i = 0; ImplicitUses[i]; ++i)
- MarkPhysRegRecentlyUsed(ImplicitUses[i]);
+ for (const unsigned *ImplicitUses = TID.ImplicitUses;
+ *ImplicitUses; ++ImplicitUses)
+ MarkPhysRegRecentlyUsed(*ImplicitUses);
// Get the used operands into registers. This has the potential to spill
// incoming values if we are out of registers. Note that we completely
diff --git a/lib/CodeGen/RegAllocSimple.cpp b/lib/CodeGen/RegAllocSimple.cpp
index 57d678b02f..dbf731ecc7 100644
--- a/lib/CodeGen/RegAllocSimple.cpp
+++ b/lib/CodeGen/RegAllocSimple.cpp
@@ -153,13 +153,13 @@ void RegAllocSimple::AllocateBasicBlock(MachineBasicBlock &MBB) {
// are used by the instruction (including implicit uses)
unsigned Opcode = MI->getOpcode();
const TargetInstrDescriptor &Desc = TM->getInstrInfo().get(Opcode);
- if (const unsigned *Regs = Desc.ImplicitUses)
- while (*Regs)
- RegsUsed[*Regs++] = true;
+ const unsigned *Regs = Desc.ImplicitUses;
+ while (*Regs)
+ RegsUsed[*Regs++] = true;
- if (const unsigned *Regs = Desc.ImplicitDefs)
- while (*Regs)
- RegsUsed[*Regs++] = true;
+ Regs = Desc.ImplicitDefs;
+ while (*Regs)
+ RegsUsed[*Regs++] = true;
// Loop over uses, move from memory into registers
for (int i = MI->getNumOperands() - 1; i >= 0; --i) {
diff --git a/utils/TableGen/InstrInfoEmitter.cpp b/utils/TableGen/InstrInfoEmitter.cpp
index c794cd0441..7b64f922f6 100644
--- a/utils/TableGen/InstrInfoEmitter.cpp
+++ b/utils/TableGen/InstrInfoEmitter.cpp
@@ -65,6 +65,10 @@ void InstrInfoEmitter::run(std::ostream &OS) {
std::vector<Record*> Instructions =
Records.getAllDerivedDefinitions("Instruction");
+ // Emit empty implicit uses and defs lists
+ OS << "static const unsigned EmptyImpUses[] = { 0 };\n"
+ << "static const unsigned EmptyImpDefs[] = { 0 };\n";
+
// Emit all of the instruction's implicit uses and defs...
for (unsigned i = 0, e = Instructions.size(); i != e; ++i) {
Record *Inst = Instructions[i];
@@ -113,13 +117,13 @@ void InstrInfoEmitter::emitRecord(Record *R, unsigned Num, Record *InstrInfo,
// Emit the implicit uses and defs lists...
LI = R->getValueAsListInit("Uses");
if (!LI->getSize())
- OS << "0, ";
+ OS << "EmptyImpUses, ";
else
OS << R->getName() << "ImpUses, ";
LI = R->getValueAsListInit("Defs");
if (!LI->getSize())
- OS << "0 ";
+ OS << "EmptyImpDefs ";
else
OS << R->getName() << "ImpDefs ";
diff --git a/utils/TableGen/RegisterInfoEmitter.cpp b/utils/TableGen/RegisterInfoEmitter.cpp
index af3efe3a9c..7652e67772 100644
--- a/utils/TableGen/RegisterInfoEmitter.cpp
+++ b/utils/TableGen/RegisterInfoEmitter.cpp
@@ -138,7 +138,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
std::vector<Record*> RegisterAliasesRecs =
Records.getAllDerivedDefinitions("RegisterAliases");
std::map<Record*, std::set<Record*> > RegisterAliases;
-
+
for (unsigned i = 0, e = RegisterAliasesRecs.size(); i != e; ++i) {
Record *AS = RegisterAliasesRecs[i];
Record *R = AS->getValueAsDef("Reg");
@@ -166,6 +166,8 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
if (!RegisterAliases.empty())
OS << "\n\n // Register Alias Sets...\n";
+ // Emit the empty alias list
+ OS << " const unsigned Empty_AliasSet[] = { 0 };\n";
// Loop over all of the registers which have aliases, emitting the alias list
// to memory.
for (std::map<Record*, std::set<Record*> >::iterator
@@ -192,7 +194,7 @@ void RegisterInfoEmitter::run(std::ostream &OS) {
if (RegisterAliases.count(Reg))
OS << Reg->getName() << "_AliasSet,\t";
else
- OS << "0,\t\t";
+ OS << "Empty_AliasSet,\t";
OS << "0, 0 },\n";
}
OS << " };\n"; // End of register descriptors...
generated by cgit v1.2.3-18-g5258 (git 2.32.0) at 2025-05-07 12:03:07 +0000