diff options
| -rw-r--r-- | lib/Target/ARM/ARMFastISel.cpp | 15 | ||||
| -rw-r--r-- | test/CodeGen/ARM/fast-isel-binary.ll | 36 |
2 files changed, 49 insertions, 2 deletions
diff --git a/lib/Target/ARM/ARMFastISel.cpp b/lib/Target/ARM/ARMFastISel.cpp index d2c8d15dbb..faa3e5920e 100644 --- a/lib/Target/ARM/ARMFastISel.cpp +++ b/lib/Target/ARM/ARMFastISel.cpp @@ -1733,7 +1733,6 @@ bool ARMFastISel::SelectRem(const Instruction *I, bool isSigned) { } bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { - assert (ISDOpcode == ISD::ADD && "Expected an add."); EVT DestVT = TLI.getValueType(I->getType(), true); // We can get here in the case when we have a binary operation on a non-legal @@ -1741,6 +1740,17 @@ bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { if (DestVT != MVT::i16 && DestVT != MVT::i8 && DestVT != MVT::i1) return false; + unsigned Opc; + switch (ISDOpcode) { + default: return false; + case ISD::ADD: + Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; + break; + case ISD::OR: + Opc = isThumb2 ? ARM::t2ORRrr : ARM::ORRrr; + break; + } + unsigned SrcReg1 = getRegForValue(I->getOperand(0)); if (SrcReg1 == 0) return false; @@ -1749,7 +1759,6 @@ bool ARMFastISel::SelectBinaryIntOp(const Instruction *I, unsigned ISDOpcode) { unsigned SrcReg2 = getRegForValue(I->getOperand(1)); if (SrcReg2 == 0) return false; - unsigned Opc = isThumb2 ? ARM::t2ADDrr : ARM::ADDrr; unsigned ResultReg = createResultReg(TLI.getRegClassFor(MVT::i32)); AddOptionalDefs(BuildMI(*FuncInfo.MBB, FuncInfo.InsertPt, DL, TII.get(Opc), ResultReg) @@ -2498,6 +2507,8 @@ bool ARMFastISel::TargetSelectInstruction(const Instruction *I) { return SelectFPToI(I, /*isSigned*/ false); case Instruction::Add: return SelectBinaryIntOp(I, ISD::ADD); + case Instruction::Or: + return SelectBinaryIntOp(I, ISD::OR); case Instruction::FAdd: return SelectBinaryFPOp(I, ISD::FADD); case Instruction::FSub: diff --git a/test/CodeGen/ARM/fast-isel-binary.ll b/test/CodeGen/ARM/fast-isel-binary.ll index 06d9cd3b3c..642fcd0355 100644 --- a/test/CodeGen/ARM/fast-isel-binary.ll +++ b/test/CodeGen/ARM/fast-isel-binary.ll @@ -38,3 +38,39 @@ entry: store i16 %0, i16* %a.addr, align 4 ret void } + +define void @or_i1(i1 %a, i1 %b) nounwind ssp { +entry: +; ARM: or_i1 +; THUMB: or_i1 + %a.addr = alloca i1, align 4 + %0 = or i1 %a, %b +; ARM: orr r0, r0, r1 +; THUMB: orrs r0, r1 + store i1 %0, i1* %a.addr, align 4 + ret void +} + +define void @or_i8(i8 %a, i8 %b) nounwind ssp { +entry: +; ARM: or_i8 +; THUMB: or_i8 + %a.addr = alloca i8, align 4 + %0 = or i8 %a, %b +; ARM: orr r0, r0, r1 +; THUMB: orrs r0, r1 + store i8 %0, i8* %a.addr, align 4 + ret void +} + +define void @or_i16(i16 %a, i16 %b) nounwind ssp { +entry: +; ARM: or_i16 +; THUMB: or_i16 + %a.addr = alloca i16, align 4 + %0 = or i16 %a, %b +; ARM: orr r0, r0, r1 +; THUMB: orrs r0, r1 + store i16 %0, i16* %a.addr, align 4 + ret void +} |