diff options
| -rw-r--r-- | include/llvm/CodeGen/SelectionDAG.h | 6 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp | 445 | ||||
| -rw-r--r-- | lib/CodeGen/SelectionDAG/SelectionDAGBuild.h | 10 |
3 files changed, 233 insertions, 228 deletions
diff --git a/include/llvm/CodeGen/SelectionDAG.h b/include/llvm/CodeGen/SelectionDAG.h index c466cf952a..f8be1679e7 100644 --- a/include/llvm/CodeGen/SelectionDAG.h +++ b/include/llvm/CodeGen/SelectionDAG.h @@ -79,9 +79,6 @@ class SelectionDAG { MachineModuleInfo *MMI; DwarfWriter *DW; - /// CurDebugLoc - current file + line number. Changes as we build the DAG. - DebugLoc CurDebugLoc; - /// EntryNode - The starting token. SDNode EntryNode; @@ -140,7 +137,6 @@ public: FunctionLoweringInfo &getFunctionLoweringInfo() const { return FLI; } MachineModuleInfo *getMachineModuleInfo() const { return MMI; } DwarfWriter *getDwarfWriter() const { return DW; } - DebugLoc getCurDebugLoc() const { return CurDebugLoc; } /// viewGraph - Pop up a GraphViz/gv window with the DAG rendered using 'dot'. /// @@ -199,8 +195,6 @@ public: return Root = N; } - void setCurDebugLoc(DebugLoc dl) { CurDebugLoc = dl; } - /// Combine - This iterates over the nodes in the SelectionDAG, folding /// certain types of nodes together, or eliminating superfluous nodes. The /// Level argument controls whether Combine is allowed to produce nodes and diff --git a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp index 3f3ce0d5b4..024cb4b92f 100644 --- a/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp +++ b/lib/CodeGen/SelectionDAG/SelectionDAGBuild.cpp @@ -216,14 +216,14 @@ namespace llvm { /// this value and returns the result as a ValueVTs value. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. - SDValue getCopyFromRegs(SelectionDAG &DAG, + SDValue getCopyFromRegs(SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const; /// getCopyToRegs - Emit a series of CopyToReg nodes that copies the /// specified value into the registers specified by this object. This uses /// Chain/Flag as the input and updates them for the output Chain/Flag. /// If the Flag pointer is NULL, no flag is used. - void getCopyToRegs(SDValue Val, SelectionDAG &DAG, + void getCopyToRegs(SDValue Val, SelectionDAG &DAG, DebugLoc dl, SDValue &Chain, SDValue *Flag) const; /// AddInlineAsmOperands - Add this value to the specified inlineasm node @@ -374,7 +374,8 @@ unsigned FunctionLoweringInfo::CreateRegForValue(const Value *V) { /// larger then ValueVT then AssertOp can be used to specify whether the extra /// bits are known to be zero (ISD::AssertZext) or sign extended from ValueVT /// (ISD::AssertSext). -static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts, +static SDValue getCopyFromParts(SelectionDAG &DAG, DebugLoc dl, + const SDValue *Parts, unsigned NumParts, MVT PartVT, MVT ValueVT, ISD::NodeType AssertOp = ISD::DELETED_NODE) { assert(NumParts > 0 && "No parts to assemble!"); @@ -400,36 +401,35 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts, MVT::getFloatingPointVT(RoundBits/2); if (RoundParts > 2) { - Lo = getCopyFromParts(DAG, Parts, RoundParts/2, PartVT, HalfVT); - Hi = getCopyFromParts(DAG, Parts+RoundParts/2, RoundParts/2, + Lo = getCopyFromParts(DAG, dl, Parts, RoundParts/2, PartVT, HalfVT); + Hi = getCopyFromParts(DAG, dl, Parts+RoundParts/2, RoundParts/2, PartVT, HalfVT); } else { - Lo = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), - HalfVT, Parts[0]); - Hi = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), - HalfVT, Parts[1]); + Lo = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[0]); + Hi = DAG.getNode(ISD::BIT_CONVERT, dl, HalfVT, Parts[1]); } if (TLI.isBigEndian()) std::swap(Lo, Hi); - Val = DAG.getNode(ISD::BUILD_PAIR, DAG.getCurDebugLoc(), RoundVT, Lo, Hi); + Val = DAG.getNode(ISD::BUILD_PAIR, dl, RoundVT, Lo, Hi); if (RoundParts < NumParts) { // Assemble the trailing non-power-of-2 part. unsigned OddParts = NumParts - RoundParts; MVT OddVT = MVT::getIntegerVT(OddParts * PartBits); - Hi = getCopyFromParts(DAG, Parts+RoundParts, OddParts, PartVT, OddVT); + Hi = getCopyFromParts(DAG, dl, + Parts+RoundParts, OddParts, PartVT, OddVT); // Combine the round and odd parts. Lo = Val; if (TLI.isBigEndian()) std::swap(Lo, Hi); MVT TotalVT = MVT::getIntegerVT(NumParts * PartBits); - Hi = DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), TotalVT, Hi); - Hi = DAG.getNode(ISD::SHL, DAG.getCurDebugLoc(), TotalVT, Hi, + Hi = DAG.getNode(ISD::ANY_EXTEND, dl, TotalVT, Hi); + Hi = DAG.getNode(ISD::SHL, dl, TotalVT, Hi, DAG.getConstant(Lo.getValueType().getSizeInBits(), TLI.getShiftAmountTy())); - Lo = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), TotalVT, Lo); - Val = DAG.getNode(ISD::OR, DAG.getCurDebugLoc(), TotalVT, Lo, Hi); + Lo = DAG.getNode(ISD::ZERO_EXTEND, dl, TotalVT, Lo); + Val = DAG.getNode(ISD::OR, dl, TotalVT, Lo, Hi); } } else { // Handle a multi-element vector. @@ -450,7 +450,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts, // If the register was not expanded, truncate or copy the value, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) - Ops[i] = getCopyFromParts(DAG, &Parts[i], 1, + Ops[i] = getCopyFromParts(DAG, dl, &Parts[i], 1, PartVT, IntermediateVT); } else if (NumParts > 0) { // If the intermediate type was expanded, build the intermediate operands @@ -459,15 +459,14 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts, "Must expand into a divisible number of parts!"); unsigned Factor = NumParts / NumIntermediates; for (unsigned i = 0; i != NumIntermediates; ++i) - Ops[i] = getCopyFromParts(DAG, &Parts[i * Factor], Factor, + Ops[i] = getCopyFromParts(DAG, dl, &Parts[i * Factor], Factor, PartVT, IntermediateVT); } // Build a vector with BUILD_VECTOR or CONCAT_VECTORS from the intermediate // operands. Val = DAG.getNode(IntermediateVT.isVector() ? - ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, - DAG.getCurDebugLoc(), + ISD::CONCAT_VECTORS : ISD::BUILD_VECTOR, dl, ValueVT, &Ops[0], NumIntermediates); } } @@ -480,14 +479,14 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts, if (PartVT.isVector()) { assert(ValueVT.isVector() && "Unknown vector conversion!"); - return DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); } if (ValueVT.isVector()) { assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && "Only trivial scalar-to-vector conversions should get here!"); - return DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::BUILD_VECTOR, dl, ValueVT, Val); } if (PartVT.isInteger() && @@ -497,24 +496,24 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts, // indicate whether the truncated bits will always be // zero or sign-extension. if (AssertOp != ISD::DELETED_NODE) - Val = DAG.getNode(AssertOp, DAG.getCurDebugLoc(), PartVT, Val, + Val = DAG.getNode(AssertOp, dl, PartVT, Val, DAG.getValueType(ValueVT)); - return DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { - return DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::ANY_EXTEND, dl, ValueVT, Val); } } if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { if (ValueVT.bitsLT(Val.getValueType())) // FP_ROUND's are always exact here. - return DAG.getNode(ISD::FP_ROUND, DAG.getCurDebugLoc(), ValueVT, Val, + return DAG.getNode(ISD::FP_ROUND, dl, ValueVT, Val, DAG.getIntPtrConstant(1)); - return DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::FP_EXTEND, dl, ValueVT, Val); } if (PartVT.getSizeInBits() == ValueVT.getSizeInBits()) - return DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), ValueVT, Val); + return DAG.getNode(ISD::BIT_CONVERT, dl, ValueVT, Val); assert(0 && "Unknown mismatch!"); return SDValue(); @@ -523,7 +522,7 @@ static SDValue getCopyFromParts(SelectionDAG &DAG, const SDValue *Parts, /// getCopyToParts - Create a series of nodes that contain the specified value /// split into legal parts. If the parts contain more bits than Val, then, for /// integers, ExtendKind can be used to specify how to generate the extra bits. -static void getCopyToParts(SelectionDAG &DAG, SDValue Val, +static void getCopyToParts(SelectionDAG &DAG, DebugLoc dl, SDValue Val, SDValue *Parts, unsigned NumParts, MVT PartVT, ISD::NodeType ExtendKind = ISD::ANY_EXTEND) { const TargetLowering &TLI = DAG.getTargetLoweringInfo(); @@ -546,22 +545,22 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, // If the parts cover more bits than the value has, promote the value. if (PartVT.isFloatingPoint() && ValueVT.isFloatingPoint()) { assert(NumParts == 1 && "Do not know what to promote to!"); - Val = DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), PartVT, Val); + Val = DAG.getNode(ISD::FP_EXTEND, dl, PartVT, Val); } else if (PartVT.isInteger() && ValueVT.isInteger()) { ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ExtendKind, DAG.getCurDebugLoc(), ValueVT, Val); + Val = DAG.getNode(ExtendKind, dl, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); } } else if (PartBits == ValueVT.getSizeInBits()) { // Different types of the same size. assert(NumParts == 1 && PartVT != ValueVT); - Val = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), PartVT, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); } else if (NumParts * PartBits < ValueVT.getSizeInBits()) { // If the parts cover less bits than value has, truncate the value. if (PartVT.isInteger() && ValueVT.isInteger()) { ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val); + Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } else { assert(0 && "Unknown mismatch!"); } @@ -586,21 +585,21 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, unsigned RoundParts = 1 << Log2_32(NumParts); unsigned RoundBits = RoundParts * PartBits; unsigned OddParts = NumParts - RoundParts; - SDValue OddVal = DAG.getNode(ISD::SRL, DAG.getCurDebugLoc(), ValueVT, Val, + SDValue OddVal = DAG.getNode(ISD::SRL, dl, ValueVT, Val, DAG.getConstant(RoundBits, TLI.getShiftAmountTy())); - getCopyToParts(DAG, OddVal, Parts + RoundParts, OddParts, PartVT); + getCopyToParts(DAG, dl, OddVal, Parts + RoundParts, OddParts, PartVT); if (TLI.isBigEndian()) // The odd parts were reversed by getCopyToParts - unreverse them. std::reverse(Parts + RoundParts, Parts + NumParts); NumParts = RoundParts; ValueVT = MVT::getIntegerVT(NumParts * PartBits); - Val = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), ValueVT, Val); + Val = DAG.getNode(ISD::TRUNCATE, dl, ValueVT, Val); } // The number of parts is a power of 2. Repeatedly bisect the value using // EXTRACT_ELEMENT. - Parts[0] = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + Parts[0] = DAG.getNode(ISD::BIT_CONVERT, dl, MVT::getIntegerVT(ValueVT.getSizeInBits()), Val); for (unsigned StepSize = NumParts; StepSize > 1; StepSize /= 2) { @@ -610,17 +609,17 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, SDValue &Part0 = Parts[i]; SDValue &Part1 = Parts[i+StepSize/2]; - Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, DAG.getCurDebugLoc(), + Part1 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, ThisVT, Part0, DAG.getConstant(1, PtrVT)); - Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, DAG.getCurDebugLoc(), + Part0 = DAG.getNode(ISD::EXTRACT_ELEMENT, dl, ThisVT, Part0, DAG.getConstant(0, PtrVT)); if (ThisBits == PartBits && ThisVT != PartVT) { - Part0 = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + Part0 = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Part0); - Part1 = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + Part1 = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Part1); } } @@ -636,12 +635,12 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, if (NumParts == 1) { if (PartVT != ValueVT) { if (PartVT.isVector()) { - Val = DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), PartVT, Val); + Val = DAG.getNode(ISD::BIT_CONVERT, dl, PartVT, Val); } else { assert(ValueVT.getVectorElementType() == PartVT && ValueVT.getVectorNumElements() == 1 && "Only trivial vector-to-scalar conversions should get here!"); - Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), + Val = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, PartVT, Val, DAG.getConstant(0, PtrVT)); } @@ -667,12 +666,12 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, SmallVector<SDValue, 8> Ops(NumIntermediates); for (unsigned i = 0; i != NumIntermediates; ++i) if (IntermediateVT.isVector()) - Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, DAG.getCurDebugLoc(), + Ops[i] = DAG.getNode(ISD::EXTRACT_SUBVECTOR, dl, IntermediateVT, Val, DAG.getConstant(i * (NumElements / NumIntermediates), PtrVT)); else - Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), + Ops[i] = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, IntermediateVT, Val, DAG.getConstant(i, PtrVT)); @@ -681,7 +680,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, // If the register was not expanded, promote or copy the value, // as appropriate. for (unsigned i = 0; i != NumParts; ++i) - getCopyToParts(DAG, Ops[i], &Parts[i], 1, PartVT); + getCopyToParts(DAG, dl, Ops[i], &Parts[i], 1, PartVT); } else if (NumParts > 0) { // If the intermediate type was expanded, split each the value into // legal parts. @@ -689,7 +688,7 @@ static void getCopyToParts(SelectionDAG &DAG, SDValue Val, "Must expand into a divisible number of parts!"); unsigned Factor = NumParts / NumIntermediates; for (unsigned i = 0; i != NumIntermediates; ++i) - getCopyToParts(DAG, Ops[i], &Parts[i * Factor], Factor, PartVT); + getCopyToParts(DAG, dl, Ops[i], &Parts[i * Factor], Factor, PartVT); } } @@ -730,7 +729,7 @@ SDValue SelectionDAGLowering::getRoot() { } // Otherwise, we have to make a token factor node. - SDValue Root = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), MVT::Other, + SDValue Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &PendingLoads[0], PendingLoads.size()); PendingLoads.clear(); DAG.setRoot(Root); @@ -760,7 +759,7 @@ SDValue SelectionDAGLowering::getControlRoot() { PendingExports.push_back(Root); } - Root = DAG.getNode(ISD::TokenFactor, DAG.getCurDebugLoc(), MVT::Other, + Root = DAG.getNode(ISD::TokenFactor, getCurDebugLoc(), MVT::Other, &PendingExports[0], PendingExports.size()); PendingExports.clear(); @@ -820,7 +819,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { if (isa<UndefValue>(C) && !isa<VectorType>(V->getType()) && !V->getType()->isAggregateType()) - return N = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), VT); + return N = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), VT); if (ConstantExpr *CE = dyn_cast<ConstantExpr>(C)) { visit(CE->getOpcode(), *CE); @@ -853,7 +852,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { for (unsigned i = 0; i != NumElts; ++i) { MVT EltVT = ValueVTs[i]; if (isa<UndefValue>(C)) - Constants[i] = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), EltVT); + Constants[i] = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT); else if (EltVT.isFloatingPoint()) Constants[i] = DAG.getConstantFP(0, EltVT); else @@ -878,7 +877,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { SDValue Op; if (isa<UndefValue>(C)) - Op = DAG.getNode(ISD::UNDEF, DAG.getCurDebugLoc(), EltVT); + Op = DAG.getNode(ISD::UNDEF, getCurDebugLoc(), EltVT); else if (EltVT.isFloatingPoint()) Op = DAG.getConstantFP(0, EltVT); else @@ -887,7 +886,7 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { } // Create a BUILD_VECTOR node. - return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, DAG.getCurDebugLoc(), + return NodeMap[V] = DAG.getNode(ISD::BUILD_VECTOR, getCurDebugLoc(), VT, &Ops[0], Ops.size()); } @@ -905,13 +904,13 @@ SDValue SelectionDAGLowering::getValue(const Value *V) { RegsForValue RFV(TLI, InReg, V->getType()); SDValue Chain = DAG.getEntryNode(); - return RFV.getCopyFromRegs(DAG, Chain, NULL); + return RFV.getCopyFromRegs(DAG, getCurDebugLoc(), Chain, NULL); } void SelectionDAGLowering::visitRet(ReturnInst &I) { if (I.getNumOperands() == 0) { - DAG.setRoot(DAG.getNode(ISD::RET, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other, getControlRoot())); return; } @@ -948,7 +947,8 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { else if (F->paramHasAttr(0, Attribute::ZExt)) ExtendKind = ISD::ZERO_EXTEND; - getCopyToParts(DAG, SDValue(RetOp.getNode(), RetOp.getResNo() + j), + getCopyToParts(DAG, getCurDebugLoc(), + SDValue(RetOp.getNode(), RetOp.getResNo() + j), &Parts[0], NumParts, PartVT, ExtendKind); // 'inreg' on function refers to return value @@ -961,7 +961,7 @@ void SelectionDAGLowering::visitRet(ReturnInst &I) { } } } - DAG.setRoot(DAG.getNode(ISD::RET, DAG.getCurDebugLoc(), MVT::Other, + DAG.setRoot(DAG.getNode(ISD::RET, getCurDebugLoc(), MVT::Other, &NewValues[0], NewValues.size())); } @@ -1201,7 +1201,7 @@ void SelectionDAGLowering::visitBr(BranchInst &I) { // If this is not a fall-through branch, emit the branch. if (Succ0MBB != NextBlock) - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, getControlRoot(), DAG.getBasicBlock(Succ0MBB))); return; @@ -1281,7 +1281,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { Cond = CondLHS; else if (CB.CmpRHS == ConstantInt::getFalse() && CB.CC == ISD::SETEQ) { SDValue True = DAG.getConstant(1, CondLHS.getValueType()); - Cond = DAG.getNode(ISD::XOR, DAG.getCurDebugLoc(), + Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), CondLHS.getValueType(), CondLHS, True); } else Cond = DAG.getSetCC(MVT::i1, CondLHS, getValue(CB.CmpRHS), CB.CC); @@ -1297,7 +1297,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { if (cast<ConstantInt>(CB.CmpLHS)->isMinValue(true)) { Cond = DAG.getSetCC(MVT::i1, CmpOp, DAG.getConstant(High, VT), ISD::SETLE); } else { - SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), + SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, CmpOp, DAG.getConstant(Low, VT)); Cond = DAG.getSetCC(MVT::i1, SUB, DAG.getConstant(High-Low, VT), ISD::SETULE); @@ -1320,10 +1320,10 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { if (CB.TrueBB == NextBlock) { std::swap(CB.TrueBB, CB.FalseBB); SDValue True = DAG.getConstant(1, Cond.getValueType()); - Cond = DAG.getNode(ISD::XOR, DAG.getCurDebugLoc(), + Cond = DAG.getNode(ISD::XOR, getCurDebugLoc(), Cond.getValueType(), Cond, True); } - SDValue BrCond = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(), + SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), MVT::Other, getControlRoot(), Cond, DAG.getBasicBlock(CB.TrueBB)); @@ -1339,7 +1339,7 @@ void SelectionDAGLowering::visitSwitchCase(CaseBlock &CB) { if (CB.FalseBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, DAG.getBasicBlock(CB.FalseBB))); } } @@ -1351,7 +1351,7 @@ void SelectionDAGLowering::visitJumpTable(JumpTable &JT) { MVT PTy = TLI.getPointerTy(); SDValue Index = DAG.getCopyFromReg(getControlRoot(), JT.Reg, PTy); SDValue Table = DAG.getJumpTable(JT.JTI, PTy); - DAG.setRoot(DAG.getNode(ISD::BR_JT, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::BR_JT, getCurDebugLoc(), MVT::Other, Index.getValue(1), Table, Index)); } @@ -1365,7 +1365,7 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, // difference between smallest and largest cases. SDValue SwitchOp = getValue(JTH.SValue); MVT VT = SwitchOp.getValueType(); - SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), VT, SwitchOp, + SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, DAG.getConstant(JTH.First, VT)); // The SDNode we just created, which holds the value being switched on minus @@ -1374,10 +1374,10 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, // This value may be smaller or larger than the target's pointer type, and // therefore require extension or truncating. if (VT.bitsGT(TLI.getPointerTy())) - SwitchOp = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), + SwitchOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), TLI.getPointerTy(), SUB); else - SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + SwitchOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), TLI.getPointerTy(), SUB); unsigned JumpTableReg = FuncInfo.MakeReg(TLI.getPointerTy()); @@ -1398,14 +1398,14 @@ void SelectionDAGLowering::visitJumpTableHeader(JumpTable &JT, if (++BBI != CurMBB->getParent()->end()) NextBlock = BBI; - SDValue BrCond = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(), + SDValue BrCond = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), MVT::Other, CopyTo, CMP, DAG.getBasicBlock(JT.Default)); if (JT.MBB == NextBlock) DAG.setRoot(BrCond); else - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrCond, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrCond, DAG.getBasicBlock(JT.MBB))); } @@ -1415,7 +1415,7 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { // Subtract the minimum value SDValue SwitchOp = getValue(B.SValue); MVT VT = SwitchOp.getValueType(); - SDValue SUB = DAG.getNode(ISD::SUB, DAG.getCurDebugLoc(), VT, SwitchOp, + SDValue SUB = DAG.getNode(ISD::SUB, getCurDebugLoc(), VT, SwitchOp, DAG.getConstant(B.First, VT)); // Check range @@ -1425,10 +1425,10 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { SDValue ShiftOp; if (VT.bitsGT(TLI.getShiftAmountTy())) - ShiftOp = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), + ShiftOp = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), TLI.getShiftAmountTy(), SUB); else - ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + ShiftOp = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), TLI.getShiftAmountTy(), SUB); B.Reg = FuncInfo.MakeReg(TLI.getShiftAmountTy()); @@ -1446,14 +1446,14 @@ void SelectionDAGLowering::visitBitTestHeader(BitTestBlock &B) { CurMBB->addSuccessor(B.Default); CurMBB->addSuccessor(MBB); - SDValue BrRange = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(), + SDValue BrRange = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), MVT::Other, CopyTo, RangeCmp, DAG.getBasicBlock(B.Default)); if (MBB == NextBlock) DAG.setRoot(BrRange); else - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, CopyTo, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, CopyTo, DAG.getBasicBlock(MBB))); } @@ -1464,13 +1464,13 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, // Make desired shift SDValue ShiftOp = DAG.getCopyFromReg(getControlRoot(), Reg, TLI.getShiftAmountTy()); - SDValue SwitchVal = DAG.getNode(ISD::SHL, DAG.getCurDebugLoc(), + SDValue SwitchVal = DAG.getNode(ISD::SHL, getCurDebugLoc(), TLI.getPointerTy(), DAG.getConstant(1, TLI.getPointerTy()), ShiftOp); // Emit bit tests and jumps - SDValue AndOp = DAG.getNode(ISD::AND, DAG.getCurDebugLoc(), + SDValue AndOp = DAG.getNode(ISD::AND, getCurDebugLoc(), TLI.getPointerTy(), SwitchVal, DAG.getConstant(B.Mask, TLI.getPointerTy())); SDValue AndCmp = DAG.getSetCC(TLI.getSetCCResultType(AndOp.getValueType()), @@ -1480,7 +1480,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, CurMBB->addSuccessor(B.TargetBB); CurMBB->addSuccessor(NextMBB); - SDValue BrAnd = DAG.getNode(ISD::BRCOND, DAG.getCurDebugLoc(), + SDValue BrAnd = DAG.getNode(ISD::BRCOND, getCurDebugLoc(), MVT::Other, getControlRoot(), AndCmp, DAG.getBasicBlock(B.TargetBB)); @@ -1494,7 +1494,7 @@ void SelectionDAGLowering::visitBitTestCase(MachineBasicBlock* NextMBB, if (NextMBB == NextBlock) DAG.setRoot(BrAnd); else - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), MVT::Other, BrAnd, + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, BrAnd, DAG.getBasicBlock(NextMBB))); } @@ -1522,7 +1522,7 @@ void SelectionDAGLowering::visitInvoke(InvokeInst &I) { CurMBB->addSuccessor(LandingPad); // Drop into normal successor. - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, getControlRoot(), DAG.getBasicBlock(Return))); } @@ -2026,7 +2026,7 @@ void SelectionDAGLowering::visitSwitch(SwitchInst &SI) { // If this is not a fall-through branch, emit the branch. CurMBB->addSuccessor(Default); if (Default != NextBlock) - DAG.setRoot(DAG.getNode(ISD::BR, DAG.getCurDebugLoc(), + DAG.setRoot(DAG.getNode(ISD::BR, getCurDebugLoc(), MVT::Other, getControlRoot(), DAG.getBasicBlock(Default))); return; @@ -2089,7 +2089,7 @@ void SelectionDAGLowering::visitSub(User &I) { Constant *CNZ = ConstantVector::get(&NZ[0], NZ.size()); if (CV == CNZ) { SDValue Op2 = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FNEG, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), Op2.getValueType(), Op2)); return; } @@ -2100,7 +2100,7 @@ void SelectionDAGLowering::visitSub(User &I) { if (ConstantFP *CFP = dyn_cast<ConstantFP>(I.getOperand(0))) if (CFP->isExactlyValue(ConstantFP::getNegativeZero(Ty)->getValueAPF())) { SDValue Op2 = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(ISD::FNEG, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FNEG, getCurDebugLoc(), Op2.getValueType(), Op2)); return; } @@ -2113,7 +2113,7 @@ void SelectionDAGLowering::visitBinary(User &I, unsigned OpCode) { SDValue Op1 = getValue(I.getOperand(0)); SDValue Op2 = getValue(I.getOperand(1)); - setValue(&I, DAG.getNode(OpCode, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(OpCode, getCurDebugLoc(), Op1.getValueType(), Op1, Op2)); } @@ -2122,14 +2122,14 @@ void SelectionDAGLowering::visitShift(User &I, unsigned Opcode) { SDValue Op2 = getValue(I.getOperand(1)); if (!isa<VectorType>(I.getType())) { if (TLI.getShiftAmountTy().bitsLT(Op2.getValueType())) - Op2 = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), + Op2 = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), TLI.getShiftAmountTy(), Op2); else if (TLI.getShiftAmountTy().bitsGT(Op2.getValueType())) - Op2 = DAG.getNode(ISD::ANY_EXTEND, DAG.getCurDebugLoc(), + Op2 = DAG.getNode(ISD::ANY_EXTEND, getCurDebugLoc(), TLI.getShiftAmountTy(), Op2); } - setValue(&I, DAG.getNode(Opcode, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(Opcode, getCurDebugLoc(), Op1.getValueType(), Op1, Op2)); } @@ -2194,12 +2194,12 @@ void SelectionDAGLowering::visitSelect(User &I) { SDValue FalseVal = getValue(I.getOperand(2)); for (unsigned i = 0; i != NumValues; ++i) - Values[i] = DAG.getNode(ISD::SELECT, DAG.getCurDebugLoc(), + Values[i] = DAG.getNode(ISD::SELECT, getCurDebugLoc(), TrueVal.getValueType(), Cond, SDValue(TrueVal.getNode(), TrueVal.getResNo() + i), SDValue(FalseVal.getNode(), FalseVal.getResNo() + i)); - setValue(&I, DAG.getNode(ISD::MERGE_VALUES, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::MERGE_VALUES, getCurDebugLoc(), DAG.getVTList(&ValueVTs[0], NumValues), &Values[0], NumValues)); } @@ -2210,7 +2210,7 @@ void SelectionDAGLowering::visitTrunc(User &I) { // TruncInst cannot be a no-op cast because sizeof(src) > sizeof(dest). SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitZExt(User &I) { @@ -2218,7 +2218,7 @@ void SelectionDAGLowering::visitZExt(User &I) { // ZExt also can't be a cast to bool for same reason. So, nothing much to do SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitSExt(User &I) { @@ -2226,14 +2226,14 @@ void SelectionDAGLowering::visitSExt(User &I) { // SExt also can't be a cast to bool for same reason. So, nothing much to do SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::SIGN_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPTrunc(User &I) { // FPTrunc is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_ROUND, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::FP_ROUND, getCurDebugLoc(), DestVT, N, DAG.getIntPtrConstant(0))); } @@ -2241,35 +2241,35 @@ void SelectionDAGLowering::visitFPExt(User &I){ // FPTrunc is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_EXTEND, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_EXTEND, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPToUI(User &I) { // FPToUI is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_TO_UINT, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_TO_UINT, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitFPToSI(User &I) { // FPToSI is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::FP_TO_SINT, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::FP_TO_SINT, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitUIToFP(User &I) { // UIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::UINT_TO_FP, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::UINT_TO_FP, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitSIToFP(User &I){ // SIToFP is never a no-op cast, no need to check SDValue N = getValue(I.getOperand(0)); MVT DestVT = TLI.getValueType(I.getType()); - setValue(&I, DAG.getNode(ISD::SINT_TO_FP, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::SINT_TO_FP, getCurDebugLoc(), DestVT, N)); } void SelectionDAGLowering::visitPtrToInt(User &I) { @@ -2280,10 +2280,10 @@ void SelectionDAGLowering::visitPtrToInt(User &I) { MVT DestVT = TLI.getValueType(I.getType()); SDValue Result; if (DestVT.bitsLT(SrcVT)) - Result = DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N); + Result = DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too - Result = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), DestVT, N); + Result = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N); setValue(&I, Result); } @@ -2294,10 +2294,10 @@ void SelectionDAGLowering::visitIntToPtr(User &I) { MVT SrcVT = N.getValueType(); MVT DestVT = TLI.getValueType(I.getType()); if (DestVT.bitsLT(SrcVT)) - setValue(&I, DAG.getNode(ISD::TRUNCATE, DAG.getCurDebugLoc(), DestVT, N)); + setValue(&I, DAG.getNode(ISD::TRUNCATE, getCurDebugLoc(), DestVT, N)); else // Note: ZERO_EXTEND can handle cases where the sizes are equal too - setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), DestVT, N)); } @@ -2308,7 +2308,7 @@ void SelectionDAGLowering::visitBitCast(User &I) { // BitCast assures us that source and destination are the same size so this // is either a BIT_CONVERT or a no-op. if (DestVT != N.getValueType()) - setValue(&I, DAG.getNode(ISD::BIT_CONVERT, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::BIT_CONVERT, getCurDebugLoc(), DestVT, N)); // convert types else setValue(&I, N); // noop cast. @@ -2317,21 +2317,21 @@ void SelectionDAGLowering::visitBitCast(User &I) { void SelectionDAGLowering::visitInsertElement(User &I) { SDValue InVec = getValue(I.getOperand(0)); SDValue InVal = getValue(I.getOperand(1)); - SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), TLI.getPointerTy(), getValue(I.getOperand(2))); - setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::INSERT_VECTOR_ELT, getCurDebugLoc(), TLI.getValueType(I.getType()), InVec, InVal, InIdx)); } void SelectionDAGLowering::visitExtractElement(User &I) { SDValue InVec = getValue(I.getOperand(0)); - SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, DAG.getCurDebugLoc(), + SDValue InIdx = DAG.getNode(ISD::ZERO_EXTEND, getCurDebugLoc(), TLI.getPointerTy(), getValue(I.getOperand(1))); - setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::EXTRACT_VECTOR_ELT, getCurDebugLoc(), TLI.getValueType(I.getType()), InVec, InIdx)); } @@ -2361,7 +2361,7 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { int SrcNumElts = SrcVT.getVectorNumElements(); if (SrcNumElts == MaskNumElts) { - setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::VECTOR_SHUFFLE, getCurDebugLoc(), VT, Src1, Src2, Mask)); return; } @@ -2375,14 +2375,14 @@ void SelectionDAGLowering::visitShuffleVector(User &I) { // lengths match. if (SrcNumElts*2 == MaskNumElts && SequentialMask(Mask, 0)) { // The shuffle is concatenating two vectors together. - setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, DAG.getCurDebugLoc(), + setValue(&I, DAG.getNode(ISD::CONCAT_VECTORS, getCurDebugLoc(), VT, Src1, Src2)); return; } // Pad both vectors with undefs to make them the same length as the mask. |