diff options
| -rw-r--r-- | lib/Target/ARM/ARMTargetMachine.cpp | 12 | ||||
| -rw-r--r-- | test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/ARM/2009-09-01-PostRAProlog.ll | 5 | ||||
| -rw-r--r-- | test/CodeGen/ARM/ifcvt5.ll | 5 |
4 files changed, 7 insertions, 17 deletions
diff --git a/lib/Target/ARM/ARMTargetMachine.cpp b/lib/Target/ARM/ARMTargetMachine.cpp index ef42bd20ca..32ddc20a56 100644 --- a/lib/Target/ARM/ARMTargetMachine.cpp +++ b/lib/Target/ARM/ARMTargetMachine.cpp @@ -22,10 +22,6 @@ #include "llvm/Target/TargetRegistry.h" using namespace llvm; -static cl::opt<bool> -LdStBeforeSched("ldstopti-before-sched2", cl::Hidden, - cl::desc("Move ld / st multiple pass before postalloc scheduling")); - static const MCAsmInfo *createMCAsmInfo(const Target &T, const StringRef &TT) { Triple TheTriple(TT); @@ -109,8 +105,7 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) - if (LdStBeforeSched) - PM.add(createARMLoadStoreOptimizationPass()); + PM.add(createARMLoadStoreOptimizationPass()); return true; } @@ -118,11 +113,8 @@ bool ARMBaseTargetMachine::addPreSched2(PassManagerBase &PM, bool ARMBaseTargetMachine::addPreEmitPass(PassManagerBase &PM, CodeGenOpt::Level OptLevel) { // FIXME: temporarily disabling load / store optimization pass for Thumb1. - if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) { - if (!LdStBeforeSched) - PM.add(createARMLoadStoreOptimizationPass()); + if (OptLevel != CodeGenOpt::None && !Subtarget.isThumb1Only()) PM.add(createIfConverterPass()); - } if (Subtarget.isThumb2()) { PM.add(createThumb2ITBlockPass()); diff --git a/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll b/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll index be78023d3c..35ca7b4c9a 100644 --- a/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll +++ b/test/CodeGen/ARM/2008-11-19-ScavengerAssert.ll @@ -1,4 +1,4 @@ -; RUN: llc < %s -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 159 +; RUN: llc < %s -mtriple=arm-apple-darwin9 -stats |& grep asm-printer | grep 154 %"struct.Adv5::Ekin<3>" = type <{ i8 }> %"struct.Adv5::X::Energyflux<3>" = type { double } diff --git a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll index 508ff5e434..f0301a8638 100644 --- a/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll +++ b/test/CodeGen/ARM/2009-09-01-PostRAProlog.ll @@ -1,8 +1,5 @@ -; XFAIL: * -; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 -post-RA-scheduler | FileCheck %s +; RUN: llvm-as < %s | llc -asm-verbose=false -O3 -relocation-model=pic -disable-fp-elim -mtriple=thumbv7-apple-darwin -mcpu=cortex-a8 | FileCheck %s - -; ModuleID = '<stdin>' target datalayout = "e-p:32:32:32-i1:8:32-i8:8:32-i16:16:32-i32:32:32-i64:32:32-f32:32:32-f64:32:32-v64:64:64-v128:128:128-a0:0:32" target triple = "thumbv7-apple-darwin9" diff --git a/test/CodeGen/ARM/ifcvt5.ll b/test/CodeGen/ARM/ifcvt5.ll index da36af8bb7..13c1603c90 100644 --- a/test/CodeGen/ARM/ifcvt5.ll +++ b/test/CodeGen/ARM/ifcvt5.ll @@ -1,5 +1,4 @@ -; RUN: llc < %s -march=arm -; RUN: llc < %s -march=arm | grep blge | count 1 +; RUN: llc < %s -march=arm | FileCheck %s @x = external global i32* ; <i32**> [#uses=1] @@ -11,6 +10,8 @@ entry: } define void @t1(i32 %a, i32 %b) { +; CHECK: t1: +; CHECK: ldmltfd sp!, {r7, pc} entry: %tmp1 = icmp sgt i32 %a, 10 ; <i1> [#uses=1] br i1 %tmp1, label %cond_true, label %UnifiedReturnBlock |