diff options
| -rw-r--r-- | lib/Target/PowerPC/PPC.td | 37 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 247 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 345 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCSchedule.td | 150 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG3.td | 6 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4.td | 6 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG4Plus.td | 6 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCScheduleG5.td | 6 | ||||
| -rw-r--r-- | lib/Target/Target.td | 13 |
9 files changed, 427 insertions, 389 deletions
diff --git a/lib/Target/PowerPC/PPC.td b/lib/Target/PowerPC/PPC.td index 4798ae8d17..36dc1641d7 100644 --- a/lib/Target/PowerPC/PPC.td +++ b/lib/Target/PowerPC/PPC.td @@ -20,8 +20,45 @@ include "../Target.td" //===----------------------------------------------------------------------===// include "PPCRegisterInfo.td" +include "PPCSchedule.td" include "PPCInstrInfo.td" + + +//===----------------------------------------------------------------------===// +// PowerPC Subtarget features. +// + +def F64Bit : SubtargetFeature<"64bit", + "Should 64 bit instructions be used">; +def F64BitRegs : SubtargetFeature<"64bitregs", + "Should 64 bit registers be used">; +def FAltivec : SubtargetFeature<"altivec", + "Should Altivec instructions be used">; +def FGPUL : SubtargetFeature<"gpul", + "Should GPUL instructions be used">; +def FFSQRT : SubtargetFeature<"fsqrt", + "Should the fsqrt instruction be used">; + +//===----------------------------------------------------------------------===// +// PowerPC chips sets supported +// + +def : Processor<"601", G3Itineraries, []>; +def : Processor<"602", G3Itineraries, []>; +def : Processor<"603", G3Itineraries, []>; +def : Processor<"604", G3Itineraries, []>; +def : Processor<"750", G3Itineraries, []>; +def : Processor<"7400", G4Itineraries, [FAltivec]>; +def : Processor<"g4", G4Itineraries, [FAltivec]>; +def : Processor<"7450", G4PlusItineraries, [FAltivec]>; +def : Processor<"g4+", G4PlusItineraries, [FAltivec]>; +def : Processor<"970", G5Itineraries, + [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; +def : Processor<"g5", G5Itineraries, + [FAltivec, FGPUL, FFSQRT, F64Bit, F64BitRegs]>; + + def PPC : Target { // Pointers on PPC are 32-bits in size. let PointerType = i32; diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 061311feaf..ee04dd62ee 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -14,7 +14,8 @@ // // PowerPC instruction formats -class I<bits<6> opcode, dag OL, string asmstr> : Instruction { +class I<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : Instruction { field bits<32> Inst; bit PPC64 = 0; // Default value, override with isPPC64 @@ -25,11 +26,13 @@ class I<bits<6> opcode, dag OL, string asmstr> : Instruction { let Inst{0-5} = opcode; let OperandList = OL; let AsmString = asmstr; + let Itinerary = itin; } // 1.7.1 I-Form -class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<24> LI; let Inst{6-29} = LI; @@ -39,8 +42,8 @@ class IForm<bits<6> opcode, bit aa, bit lk, dag OL, string asmstr> // 1.7.2 B-Form class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL, - string asmstr> - : I<opcode, OL, asmstr> { + string asmstr, InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<3> CR; bits<14> BD; @@ -53,8 +56,9 @@ class BForm<bits<6> opcode, bit aa, bit lk, bits<5> bo, bits<2> bicode, dag OL, } // 1.7.4 D-Form -class DForm_base<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> - : I<opcode, OL, asmstr> { +class DForm_base<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, + list<dag> pattern> + : I<opcode, OL, asmstr, itin> { let Pattern = pattern; bits<5> A; bits<5> B; @@ -65,8 +69,8 @@ class DForm_base<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> let Inst{16-31} = C; } -class DForm_1<bits<6> opcode, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class DForm_1<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> A; bits<16> C; bits<5> B; @@ -76,11 +80,13 @@ class DForm_1<bits<6> opcode, dag OL, string asmstr> let Inst{16-31} = C; } -class DForm_2<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> - : DForm_base<opcode, OL, asmstr, pattern>; +class DForm_2<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, + list<dag> pattern> + : DForm_base<opcode, OL, asmstr, itin, pattern>; -class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> - : I<opcode, OL, asmstr> { +class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, + list<dag> pattern> + : I<opcode, OL, asmstr, itin> { bits<5> A; bits<16> B; @@ -92,11 +98,12 @@ class DForm_2_r0<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> } // Currently we make the use/def reg distinction in ISel, not tablegen -class DForm_3<bits<6> opcode, dag OL, string asmstr> - : DForm_1<opcode, OL, asmstr>; +class DForm_3<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : DForm_1<opcode, OL, asmstr, itin>; -class DForm_4<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> - : I<opcode, OL, asmstr> { +class DForm_4<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin, + list<dag> pattern> + : I<opcode, OL, asmstr, itin> { bits<5> B; bits<5> A; bits<16> C; @@ -108,14 +115,15 @@ class DForm_4<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> let Inst{16-31} = C; } -class DForm_4_zero<bits<6> opcode, dag OL, string asmstr> - : DForm_1<opcode, OL, asmstr> { +class DForm_4_zero<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : DForm_1<opcode, OL, asmstr, itin> { let A = 0; let B = 0; let C = 0; } -class DForm_5<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> { +class DForm_5<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<3> BF; bits<1> L; bits<5> RA; @@ -128,30 +136,31 @@ class DForm_5<bits<6> opcode, dag OL, string asmstr> : I<opcode, OL, asmstr> { let Inst{16-31} = I; } -class DForm_5_ext<bits<6> opcode, dag OL, string asmstr> - : DForm_5<opcode, OL, asmstr> { +class DForm_5_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : DForm_5<opcode, OL, asmstr, itin> { let L = PPC64; } -class DForm_6<bits<6> opcode, dag OL, string asmstr> - : DForm_5<opcode, OL, asmstr>; +class DForm_6<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : DForm_5<opcode, OL, asmstr, itin>; -class DForm_6_ext<bits<6> opcode, dag OL, string asmstr> - : DForm_6<opcode, OL, asmstr> { +class DForm_6_ext<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : DForm_6<opcode, OL, asmstr, itin> { let L = PPC64; } -class DForm_8<bits<6> opcode, dag OL, string asmstr> - : DForm_1<opcode, OL, asmstr> { +class DForm_8<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : DForm_1<opcode, OL, asmstr, itin> { } -class DForm_9<bits<6> opcode, dag OL, string asmstr> - : DForm_1<opcode, OL, asmstr> { +class DForm_9<bits<6> opcode, dag OL, string asmstr, InstrItinClass itin> + : DForm_1<opcode, OL, asmstr, itin> { } // 1.7.5 DS-Form -class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> RST; bits<14> DS; bits<5> RA; @@ -162,12 +171,14 @@ class DSForm_1<bits<6> opcode, bits<2> xo, dag OL, string asmstr> let Inst{30-31} = xo; } -class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr> - : DSForm_1<opcode, xo, OL, asmstr>; +class DSForm_2<bits<6> opcode, bits<2> xo, dag OL, string asmstr, + InstrItinClass itin> + : DSForm_1<opcode, xo, OL, asmstr, itin>; // 1.7.6 X-Form class XForm_base_r3xo<bits<6> opcode, bits<10> xo, - dag OL, string asmstr> : I<opcode, OL, asmstr> { + dag OL, string asmstr, InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> RST; bits<5> A; bits<5> B; @@ -184,8 +195,9 @@ class XForm_base_r3xo<bits<6> opcode, bits<10> xo, // This is the same as XForm_base_r3xo, but the first two operands are swapped // when code is emitted. class XForm_base_r3xo_swapped - <bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { + <bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> A; bits<5> RST; bits<5> B; @@ -200,32 +212,36 @@ class XForm_base_r3xo_swapped } -class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : XForm_base_r3xo<opcode, xo, OL, asmstr>; +class XForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : XForm_base_r3xo<opcode, xo, OL, asmstr, itin>; -class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr, - list<dag> pattern> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> { +class XForm_6<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { let Pattern = pattern; } -class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : XForm_base_r3xo<opcode, xo, OL, asmstr>; +class XForm_8<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : XForm_base_r3xo<opcode, xo, OL, asmstr, itin>; -class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr, list<dag> pt> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> { - let Pattern = pt; +class XForm_10<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { + let Pattern = pattern; } class XForm_11<bits<6> opcode, bits<10> xo, dag OL, string asmstr, - list<dag> pattern> - : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr> { + InstrItinClass itin, list<dag> pattern> + : XForm_base_r3xo_swapped<opcode, xo, OL, asmstr, itin> { let B = 0; let Pattern = pattern; } -class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<3> BF; bits<1> L; bits<5> RA; @@ -240,13 +256,15 @@ class XForm_16<bits<6> opcode, bits<10> xo, dag OL, string asmstr> let Inst{31} = 0; } -class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : XForm_16<opcode, xo, OL, asmstr> { +class XForm_16_ext<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : XForm_16<opcode, xo, OL, asmstr, itin> { let L = PPC64; } -class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<3> BF; bits<5> FRA; bits<5> FRB; @@ -259,23 +277,27 @@ class XForm_17<bits<6> opcode, bits<10> xo, dag OL, string asmstr> let Inst{31} = 0; } -class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : XForm_base_r3xo<opcode, xo, OL, asmstr> { +class XForm_25<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> { } -class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr, list<dag> pt> - : XForm_base_r3xo<opcode, xo, OL, asmstr> { +class XForm_26<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> { let A = 0; - let Pattern = pt; + let Pattern = pattern; } -class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : XForm_base_r3xo<opcode, xo, OL, asmstr> { +class XForm_28<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : XForm_base_r3xo<opcode, xo, OL, asmstr, itin> { } // 1.7.7 XL-Form -class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<3> CRD; bits<2> CRDb; bits<3> CRA; @@ -293,8 +315,9 @@ class XLForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr> let Inst{31} = 0; } -class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, - dag OL, string asmstr> : I<opcode, OL, asmstr> { +class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> BO; bits<5> BI; bits<2> BH; @@ -307,16 +330,17 @@ class XLForm_2<bits<6> opcode, bits<10> xo, bit lk, let Inst{31} = lk; } -class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, - bits<5> bi, bit lk, dag OL, string asmstr> - : XLForm_2<opcode, xo, lk, OL, asmstr> { +class XLForm_2_ext<bits<6> opcode, bits<10> xo, bits<5> bo, bits<5> bi, bit lk, + dag OL, string asmstr, InstrItinClass itin> + : XLForm_2<opcode, xo, lk, OL, asmstr, itin> { let BO = bo; let BI = bi; let BH = 0; } -class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<3> BF; bits<3> BFA; @@ -330,8 +354,9 @@ class XLForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr> } // 1.7.8 XFX-Form -class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> RT; bits<10> SPR; @@ -342,13 +367,14 @@ class XFXForm_1<bits<6> opcode, bits<10> xo, dag OL, string asmstr> } class XFXForm_1_ext<bits<6> opcode, bits<10> xo, bits<10> spr, - dag OL, string asmstr> - : XFXForm_1<opcode, xo, OL, asmstr> { + dag OL, string asmstr, InstrItinClass itin> + : XFXForm_1<opcode, xo, OL, asmstr, itin> { let SPR = spr; } -class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> RT; let Inst{6-10} = RT; @@ -357,8 +383,9 @@ class XFXForm_3<bits<6> opcode, bits<10> xo, dag OL, string asmstr> let Inst{31} = 0; } -class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<8> FXM; bits<5> ST; @@ -370,8 +397,9 @@ class XFXForm_5<bits<6> opcode, bits<10> xo, dag OL, string asmstr> let Inst{31} = 0; } -class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> ST; bits<8> FXM; @@ -384,18 +412,20 @@ class XFXForm_5a<bits<6> opcode, bits<10> xo, dag OL, string asmstr> } -class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr> - : XFXForm_1<opcode, xo, OL, asmstr>; +class XFXForm_7<bits<6> opcode, bits<10> xo, dag OL, string asmstr, + InstrItinClass itin> + : XFXForm_1<opcode, xo, OL, asmstr, itin>; class XFXForm_7_ext<bits<6> opcode, bits<10> xo, bits<10> spr, - dag OL, string asmstr> - : XFXForm_7<opcode, xo, OL, asmstr> { + dag OL, string asmstr, InstrItinClass itin> + : XFXForm_7<opcode, xo, OL, asmstr, itin> { let SPR = spr; } // 1.7.10 XS-Form -class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr> - : I<opcode, OL, asmstr> { +class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr, + InstrItinClass itin> + : I<opcode, OL, asmstr, itin> { bits<5> RS; bits<5> A; bits<6> SH; @@ -412,8 +442,8 @@ class XSForm_1<bits<6> opcode, bits<9> xo, dag OL, string asmstr> // 1.7.11 XO-Form class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr, - list<dag> pattern> - : I<opcode, OL, asmstr> { + InstrItinClass itin, list<dag> pattern> + : I<opcode, OL, asmstr, itin> { bits<5> RT; bits<5> RA; bits<5> RB; @@ -431,15 +461,15 @@ class XOForm_1<bits<6> opcode, bits<9> xo, bit oe, dag OL, string asmstr, } class XOForm_3<bits<6> opcode, bits<9> xo, bit oe, - dag OL, string asmstr, list<dag> pattern> - : XOForm_1<opcode, xo, oe, OL, asmstr, pattern> { + dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> + : XOForm_1<opcode, xo, oe, OL, asmstr, itin, pattern> { let RB = 0; } // 1.7.12 A-Form class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr, - list<dag> pattern> - : I<opcode, OL, asmstr> { + InstrItinClass itin, list<dag> pattern> + : I<opcode, OL, asmstr, itin> { bits<5> FRT; bits<5> FRA; bits<5> FRC; @@ -457,19 +487,22 @@ class AForm_1<bits<6> opcode, bits<5> xo, dag OL, string asmstr, let Inst{31} = RC; } -class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr, list<dag> pat> - : AForm_1<opcode, xo, OL, asmstr, pat> { +class AForm_2<bits<6> opcode, bits<5> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : AForm_1<opcode, xo, OL, asmstr, itin, pattern> { let FRC = 0; } -class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr, list<dag> pat> - : AForm_1<opcode, xo, OL, asmstr, pat> { +class AForm_3<bits<6> opcode, bits<5> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : AForm_1<opcode, xo, OL, asmstr, itin, pattern> { let FRB = 0; } // 1.7.13 M-Form -class MForm_1<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> - : I<opcode, OL, asmstr> { +class MForm_1<bits<6> opcode, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OL, asmstr, itin> { bits<5> RA; bits<5> RS; bits<5> RB; @@ -488,14 +521,15 @@ class MForm_1<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> let Inst{31} = RC; } -class MForm_2<bits<6> opcode, dag OL, string asmstr, list<dag> pattern> - : MForm_1<opcode, OL, asmstr, pattern> { +class MForm_2<bits<6> opcode, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : MForm_1<opcode, OL, asmstr, itin, pattern> { } // 1.7.14 MD-Form -class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, - list<dag> pattern> - : I<opcode, OL, asmstr> { +class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : I<opcode, OL, asmstr, itin> { bits<5> RS; bits<5> RA; bits<6> SH; @@ -515,8 +549,9 @@ class MDForm_1<bits<6> opcode, bits<3> xo, dag OL, string asmstr, } //===----------------------------------------------------------------------===// - -class Pseudo<dag OL, string asmstr> : I<0, OL, asmstr> { +def NoItin : InstrItinClass; +class Pseudo<dag OL, string asmstr> + : I<0, OL, asmstr, NoItin> { let PPC64 = 0; let VMX = 0; diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 6e7408fcb2..64e3efaf36 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -159,8 +159,8 @@ let usesCustomDAGSchedInserter = 1 in { // Expanded by the scheduler. let isTerminator = 1 in { let isReturn = 1 in - def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr">; - def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr">; + def BLR : XLForm_2_ext<19, 16, 20, 0, 0, (ops), "blr", BrB>; + def BCTR : XLForm_2_ext<19, 528, 20, 0, 0, (ops), "bctr", BrB>; } let Defs = [LR] in @@ -170,25 +170,25 @@ let isBranch = 1, isTerminator = 1 in { def COND_BRANCH : Pseudo<(ops CRRC:$crS, u16imm:$opc, target:$true, target:$false), "; COND_BRANCH">; - def B : IForm<18, 0, 0, (ops target:$func), "b $func">; -//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func">; - def BL : IForm<18, 0, 1, (ops target:$func), "bl $func">; -//def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func">; + def B : IForm<18, 0, 0, (ops target:$func), "b $func", BrB>; +//def BA : IForm<18, 1, 0, (ops target:$func), "ba $func", BrB>; + def BL : IForm<18, 0, 1, (ops target:$func), "bl $func", BrB>; +//def BLA : IForm<18, 1, 1, (ops target:$func), "bla $func", BrB>; // FIXME: 4*CR# needs to be added to the BI field! // This will only work for CR0 as it stands now def BLT : BForm<16, 0, 0, 12, 0, (ops CRRC:$crS, target:$block), - "blt $crS, $block">; + "blt $crS, $block", BrB>; def BLE : BForm<16, 0, 0, 4, 1, (ops CRRC:$crS, target:$block), - "ble $crS, $block">; + "ble $crS, $block", BrB>; def BEQ : BForm<16, 0, 0, 12, 2, (ops CRRC:$crS, target:$block), - "beq $crS, $block">; + "beq $crS, $block", BrB>; def BGE : BForm<16, 0, 0, 4, 0, (ops CRRC:$crS, target:$block), - "bge $crS, $block">; + "bge $crS, $block", BrB>; def BGT : BForm<16, 0, 0, 12, 1, (ops CRRC:$crS, target:$block), - "bgt $crS, $block">; + "bgt $crS, $block", BrB>; def BNE : BForm<16, 0, 0, 4, 2, (ops CRRC:$crS, target:$block), - "bne $crS, $block">; + "bne $crS, $block", BrB>; } let isCall = 1, @@ -198,9 +198,10 @@ let isCall = 1, LR,CTR, CR0,CR1,CR5,CR6,CR7] in { // Convenient aliases for call instructions - def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), "bl $func">; + def CALLpcrel : IForm<18, 0, 1, (ops target:$func, variable_ops), + "bl $func", BrB>; def CALLindirect : XLForm_2_ext<19, 528, 20, 0, 1, - (ops variable_ops), "bctrl">; + (ops variable_ops), "bctrl", BrB>; } // D-Form instructions. Most instructions that perform an operation on a @@ -208,114 +209,114 @@ let isCall = 1, // let isLoad = 1 in { def LBZ : DForm_1<34, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), - "lbz $rD, $disp($rA)">; + "lbz $rD, $disp($rA)", LdStGeneral>; def LHA : DForm_1<42, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), - "lha $rD, $disp($rA)">; + "lha $rD, $disp($rA)", LdStLHA>; def LHZ : DForm_1<40, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), - "lhz $rD, $disp($rA)">; + "lhz $rD, $disp($rA)", LdStGeneral>; def LMW : DForm_1<46, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), - "lmw $rD, $disp($rA)">; + "lmw $rD, $disp($rA)", LdStLMW>; def LWZ : DForm_1<32, (ops GPRC:$rD, symbolLo:$disp, GPRC:$rA), - "lwz $rD, $disp($rA)">; + "lwz $rD, $disp($rA)", LdStGeneral>; def LWZU : DForm_1<35, (ops GPRC:$rD, s16imm:$disp, GPRC:$rA), - "lwzu $rD, $disp($rA)">; + "lwzu $rD, $disp($rA)", LdStGeneral>; } def ADDI : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), - "addi $rD, $rA, $imm", + "addi $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (add GPRC:$rA, immSExt16:$imm))]>; def ADDIC : DForm_2<12, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), - "addic $rD, $rA, $imm", + "addic $rD, $rA, $imm", IntGeneral, []>; def ADDICo : DForm_2<13, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), - "addic. $rD, $rA, $imm", + "addic. $rD, $rA, $imm", IntGeneral, []>; def ADDIS : DForm_2<15, (ops GPRC:$rD, GPRC:$rA, symbolHi:$imm), - "addis $rD, $rA, $imm", + "addis $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (add GPRC:$rA, imm16Shifted:$imm))]>; def LA : DForm_2<14, (ops GPRC:$rD, GPRC:$rA, symbolLo:$sym), - "la $rD, $sym($rA)", + "la $rD, $sym($rA)", IntGeneral, []>; def MULLI : DForm_2< 7, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), - "mulli $rD, $rA, $imm", + "mulli $rD, $rA, $imm", IntMulLI, [(set GPRC:$rD, (mul GPRC:$rA, immSExt16:$imm))]>; def SUBFIC : DForm_2< 8, (ops GPRC:$rD, GPRC:$rA, s16imm:$imm), - "subfic $rD, $rA, $imm", + "subfic $rD, $rA, $imm", IntGeneral, [(set GPRC:$rD, (sub immSExt16:$imm, GPRC:$rA))]>; def LI : DForm_2_r0<14, (ops GPRC:$rD, s16imm:$imm), - "li $rD, $imm", + "li $rD, $imm", IntGeneral, [(set GPRC:$rD, immSExt16:$imm)]>; def LIS : DForm_2_r0<15, (ops GPRC:$rD, symbolHi:$imm), - "lis $rD, $imm", + "lis $rD, $imm", IntGeneral, [(set GPRC:$rD, imm16Shifted:$imm)]>; let isStore = 1 in { def STMW : DForm_3<47, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), - "stmw $rS, $disp($rA)">; + "stmw $rS, $disp($rA)", LdStLMW>; def STB : DForm_3<38, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA), - "stb $rS, $disp($rA)">; + "stb $rS, $disp($rA)", LdStGeneral>; def STH : DForm_3<44, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA), - "sth $rS, $disp($rA)">; + "sth $rS, $disp($rA)", LdStGeneral>; def STW : DForm_3<36, (ops GPRC:$rS, symbolLo:$disp, GPRC:$rA), - "stw $rS, $disp($rA)">; + "stw $rS, $disp($rA)", LdStGeneral>; def STWU : DForm_3<37, (ops GPRC:$rS, s16imm:$disp, GPRC:$rA), - "stwu $rS, $disp($rA)">; + "stwu $rS, $disp($rA)", LdStGeneral>; } def ANDIo : DForm_4<28, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), - "andi. $dst, $src1, $src2", + "andi. $dst, $src1, $src2", IntGeneral, []>, isDOT; def ANDISo : DForm_4<29, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), - "andis. $dst, $src1, $src2", + "andis. $dst, $src1, $src2", IntGeneral, []>, isDOT; def ORI : DForm_4<24, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), - "ori $dst, $src1, $src2", + "ori $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (or GPRC:$src1, immZExt16:$src2))]>; def ORIS : DForm_4<25, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), - "oris $dst, $src1, $src2", + "oris $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (or GPRC:$src1, imm16Shifted:$src2))]>; def XORI : DForm_4<26, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), - "xori $dst, $src1, $src2", + "xori $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (xor GPRC:$src1, immZExt16:$src2))]>; def XORIS : DForm_4<27, (ops GPRC:$dst, GPRC:$src1, u16imm:$src2), - "xoris $dst, $src1, $src2", + "xoris $dst, $src1, $src2", IntGeneral, [(set GPRC:$dst, (xor GPRC:$src1, imm16Shifted:$src2))]>; -def NOP : DForm_4_zero<24, (ops), "nop">; +def NOP : DForm_4_zero<24, (ops), "nop", IntGeneral>; def CMPI : DForm_5<11, (ops CRRC:$crD, i1imm:$L, GPRC:$rA, s16imm:$imm), - "cmpi $crD, $L, $rA, $imm">; + "cmpi $crD, $L, $rA, $imm", IntCompare>; def CMPWI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), - "cmpwi $crD, $rA, $imm">; + "cmpwi $crD, $rA, $imm", IntCompare>; def CMPDI : DForm_5_ext<11, (ops CRRC:$crD, GPRC:$rA, s16imm:$imm), - "cmpdi $crD, $rA, $imm">, isPPC64; + "cmpdi $crD, $rA, $imm", IntCompare>, isPPC64; def CMPLI : DForm_6<10, (ops CRRC:$dst, i1imm:$size, GPRC:$src1, u16imm:$src2), - "cmpli $dst, $size, $src1, $src2">; + "cmpli $dst, $size, $src1, $src2", IntCompare>; def CMPLWI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), - "cmplwi $dst, $src1, $src2">; + "cmplwi $dst, $src1, $src2", IntCompare>; def CMPLDI : DForm_6_ext<10, (ops CRRC:$dst, GPRC:$src1, u16imm:$src2), - "cmpldi $dst, $src1, $src2">, isPPC64; + "cmpldi $dst, $src1, $src2", IntCompare>, isPPC64; let isLoad = 1 in { def LFS : DForm_8<48, (ops F4RC:$rD, symbolLo:$disp, GPRC:$rA), - "lfs $rD, $disp($rA)">; + "lfs $rD, $disp($rA)", LdStLFDU>; def LFD : DForm_8<50, (ops F8RC:$rD, symbolLo:$disp, GPRC:$rA), - "lfd $rD, $disp($rA)">; + "lfd $rD, $disp($rA)", LdStLFD>; } let isStore = 1 in { def STFS : DForm_9<52, (ops F4RC:$rS, symbolLo:$disp, GPRC:$rA), - "stfs $rS, $disp($rA)">; + "stfs $rS, $disp($rA)", LdStUX>; def STFD : DForm_9<54, (ops F8RC:$rS, symbolLo:$disp, GPRC:$rA), - "stfd $rS, $disp($rA)">; + "stfd $rS, $disp($rA)", LdStUX>; } // DS-Form instructions. Load/Store instructions available in PPC-64 // let isLoad = 1 in { def LWA : DSForm_1<58, 2, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), - "lwa $rT, $DS($rA)">, isPPC64; + "lwa $rT, $DS($rA)", LdStLWA>, isPPC64; def LD : DSForm_2<58, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), - "ld $rT, $DS($rA)">, isPPC64; + "ld $rT, $DS($rA)", LdStLD>, isPPC64; } let isStore = 1 in { def STD : DSForm_2<62, 0, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), - "std $rT, $DS($rA)">, isPPC64; + "std $rT, $DS($rA)", LdStSTD>, isPPC64; def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), - "stdu $rT, $DS($rA)">, isPPC64; + "stdu $rT, $DS($rA)", LdStSTD>, isPPC64; } // X-Form instructions. Most instructions that perform an operation on a @@ -323,270 +324,270 @@ def STDU : DSForm_2<62, 1, (ops GPRC:$rT, s16immX4:$DS, GPRC:$rA), // let isLoad = 1 in { def LBZX : XForm_1<31, 87, (ops GPRC:$dst, GPRC:$base, GPRC:$index), - "lbzx $dst, $base, $index">; + "lbzx $dst, $base, $index", LdStGeneral>; def LHAX : XForm_1<31, 343, (ops GPRC:$dst, GPRC:$base, GPRC:$index), - "lhax $dst, $base, $index">; + "lhax $dst, $base, $index", LdStLHA>; def LHZX : XForm_1<31, 279, (ops GPRC:$dst, GPRC:$base, GPRC:$index), - "lhzx $dst, $base, $index">; + "lhzx $dst, $base, $index", LdStGeneral>; def LWAX : XForm_1<31, 341, (ops GPRC:$dst, GPRC:$base, GPRC:$index), - "lwax $dst, $base, $index">, isPPC64; + "lwax $dst, $base, $index", LdStLHA>, isPPC64; def LWZX : XForm_1<31, 23, (ops GPRC:$dst, GPRC:$base, GPRC:$index), - "lwzx $dst, $base, $index">; + "lwzx $dst, $base, $index", LdStGeneral>; def LDX : XForm_1<31, 21, (ops GPRC:$dst, GPRC:$base, GPRC:$index), - "ldx $dst, $base, $index">, isPPC64; + "ldx $dst, $base, $index", LdStLD>, isPPC64; } def NAND : XForm_6<31, 476, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), - "nand $rA, $rS, $rB", + "nand $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (not (and GPRC:$rS, GPRC:$rB)))]>; def AND : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), - "and $rA, $rS, $rB", + "and $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (and GPRC:$rS, GPRC:$rB))]>; def ANDo : XForm_6<31, 28, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), - "and. $rA, $rS, $rB", + "and. $rA, $rS, $rB", IntGeneral, []>, isDOT; def ANDC : XForm_6<31, 60, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), - "andc $rA, $rS, $rB", + "andc $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (and GPRC:$rS, (not GPRC:$rB)))]>; def OR4 : XForm_6<31, 444, (ops GPRC:$rA, GPRC:$rS, GPRC:$rB), - "or $rA, $rS, $rB", + "or $rA, $rS, $rB", IntGeneral, [(set GPRC:$rA, (or GPRC:$rS, GPRC:$rB))]>; def OR8 : XForm_6<31, 444, (ops G8RC:$rA, G8RC:$rS, G8RC:$rB), |