diff options
| -rw-r--r-- | lib/Target/ARM/ARMInstrInfo.td | 2 | ||||
| -rw-r--r-- | test/MC/ARM/basic-thumb2-instructions.s | 18 |
2 files changed, 20 insertions, 0 deletions
diff --git a/lib/Target/ARM/ARMInstrInfo.td b/lib/Target/ARM/ARMInstrInfo.td index c5e4b8653c..1a5acfe1cc 100644 --- a/lib/Target/ARM/ARMInstrInfo.td +++ b/lib/Target/ARM/ARMInstrInfo.td @@ -4950,6 +4950,8 @@ def : MnemonicAlias<"saddsubx", "sasx">; def : MnemonicAlias<"shaddsubx", "shasx">; // SHSAX == SHSUBADDX def : MnemonicAlias<"shsubaddx", "shsax">; +// SSAX == SSUBADDX +def : MnemonicAlias<"ssubaddx", "ssax">; // LDRSBT/LDRHT/LDRSHT post-index offset if optional. // Note that the write-back output register is a dummy operand for MC (it's diff --git a/test/MC/ARM/basic-thumb2-instructions.s b/test/MC/ARM/basic-thumb2-instructions.s index d960f1ef29..d44d65da46 100644 --- a/test/MC/ARM/basic-thumb2-instructions.s +++ b/test/MC/ARM/basic-thumb2-instructions.s @@ -2075,6 +2075,24 @@ _func: @------------------------------------------------------------------------------ +@ SSAX +@------------------------------------------------------------------------------ + ssubaddx r2, r3, r4 + it lt + ssubaddxlt r2, r3, r4 + ssax r2, r3, r4 + it lt + ssaxlt r2, r3, r4 + +@ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2] +@ CHECK: it lt @ encoding: [0xb8,0xbf] +@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2] +@ CHECK: ssax r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2] +@ CHECK: it lt @ encoding: [0xb8,0xbf] +@ CHECK: ssaxlt r2, r3, r4 @ encoding: [0xe3,0xfa,0x04,0xf2] + + +@------------------------------------------------------------------------------ @ SUB (register) @------------------------------------------------------------------------------ sub.w r5, r2, r12, rrx |