diff options
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrFormats.td | 8 | ||||
| -rw-r--r-- | lib/Target/PowerPC/PPCInstrInfo.td | 13 |
2 files changed, 21 insertions, 0 deletions
diff --git a/lib/Target/PowerPC/PPCInstrFormats.td b/lib/Target/PowerPC/PPCInstrFormats.td index 96c969b4d0..8b28e5f814 100644 --- a/lib/Target/PowerPC/PPCInstrFormats.td +++ b/lib/Target/PowerPC/PPCInstrFormats.td @@ -602,6 +602,14 @@ class VXForm_1<bits<11> xo, dag OL, string asmstr, let Inst{21-31} = xo; } +class VXForm_setzero<bits<11> xo, dag OL, string asmstr, + InstrItinClass itin, list<dag> pattern> + : VXForm_1<xo, OL, asmstr, itin, pattern> { + let VA = VD; + let VB = VD; +} + + class VXForm_2<bits<11> xo, dag OL, string asmstr, InstrItinClass itin, list<dag> pattern> : I<4, OL, asmstr, itin> { diff --git a/lib/Target/PowerPC/PPCInstrInfo.td b/lib/Target/PowerPC/PPCInstrInfo.td index 3ea0920289..1a30985975 100644 --- a/lib/Target/PowerPC/PPCInstrInfo.td +++ b/lib/Target/PowerPC/PPCInstrInfo.td @@ -897,6 +897,16 @@ def VRSQRTEFP : VXForm_2<330, (ops VRRC:$vD, VRRC:$vB), def VSUBFP : VXForm_1<74, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), "vsubfp $vD, $vA, $vB", VecFP, [(set VRRC:$vD, (fsub VRRC:$vA, VRRC:$vB))]>; +def VXOR : VXForm_1<1220, (ops VRRC:$vD, VRRC:$vA, VRRC:$vB), + "vxor $vD, $vA, $vB", VecFP, + []>; + +// VX-Form Pseudo Instructions + +def V_SET0 : VXForm_setzero<1220, (ops VRRC:$vD), + "vxor $vD, $vD, $vD", VecFP, + []>; + //===----------------------------------------------------------------------===// // PowerPC Instruction Patterns @@ -951,6 +961,9 @@ def : Pat<(add GPRC:$in, (PPChi tglobaladdr:$g, 0)), def : Pat<(add GPRC:$in, (PPChi tconstpool:$g, 0)), (ADDIS GPRC:$in, tconstpool:$g)>; +def : Pat<(fmul VRRC:$vA, VRRC:$vB), + (VMADDFP VRRC:$vA, (V_SET0), VRRC:$vB)>; + // Fused multiply add and multiply sub for packed float. These are represented // separately from the real instructions above, for operations that must have // the additional precision, such as Newton-Rhapson (used by divide, sqrt) |