diff options
| -rw-r--r-- | lib/Target/Alpha/AlphaISelPattern.cpp | 7 | ||||
| -rw-r--r-- | lib/Target/Alpha/AlphaRegisterInfo.td | 6 |
2 files changed, 8 insertions, 5 deletions
diff --git a/lib/Target/Alpha/AlphaISelPattern.cpp b/lib/Target/Alpha/AlphaISelPattern.cpp index e2610c4406..9c9b3d6db0 100644 --- a/lib/Target/Alpha/AlphaISelPattern.cpp +++ b/lib/Target/Alpha/AlphaISelPattern.cpp @@ -179,6 +179,10 @@ namespace { { BuildMI(BB, Alpha::BIS, 2, Alpha::R26).addReg(RA).addReg(RA); } + unsigned getRA() + { + return RA; + } }; } @@ -2310,8 +2314,7 @@ void AlphaISel::Select(SDOperand N) { Select(N.getOperand(0)); break; } - AlphaLowering.restoreRA(BB); - BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(Alpha::R26); // Just emit a 'ret' instruction + BuildMI(BB, Alpha::RET, 1, Alpha::R31).addReg(AlphaLowering.getRA()); // Just emit a 'ret' instruction return; case ISD::TRUNCSTORE: diff --git a/lib/Target/Alpha/AlphaRegisterInfo.td b/lib/Target/Alpha/AlphaRegisterInfo.td index 7957bedbf7..8ead9760f8 100644 --- a/lib/Target/Alpha/AlphaRegisterInfo.td +++ b/lib/Target/Alpha/AlphaRegisterInfo.td @@ -78,14 +78,14 @@ def F30 : FPR<30, "$f30">; def F31 : FPR<31, "$f31">; // $28 is undefined after any and all calls /// Register classes +// Don't allocate 15, 28, 30, 31 def GPRC : RegisterClass<i64, 64, // Volatile [R0, R1, R2, R3, R4, R5, R6, R7, R8, R16, R17, R18, R19, R20, R21, R22, - R23, R24, R25, R27, + R23, R24, R25, R26, R27, // Non-volatile - R9, R10, R11, R12, R13, R14, /*R15,*/ R26, /* R28, */ R29 /* R30, R31*/ ]>; + R9, R10, R11, R12, R13, R14, R29 ]>; // Note: R28 is reserved for the assembler - //leave FP alone // Don't allocate 15, 29, 30, 31 // Allocation volatiles only for now |