diff options
| -rw-r--r-- | lib/Target/X86/X86InstrInfo.td | 1532 |
1 files changed, 963 insertions, 569 deletions
diff --git a/lib/Target/X86/X86InstrInfo.td b/lib/Target/X86/X86InstrInfo.td index 2cab50b62f..b080b5e29d 100644 --- a/lib/Target/X86/X86InstrInfo.td +++ b/lib/Target/X86/X86InstrInfo.td @@ -77,7 +77,8 @@ def CondMovFP : FPFormat<6>; def SpecialFP : FPFormat<7>; -class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> : Instruction { +class X86Inst<bits<8> opcod, Format f, ImmType i, dag ops, string AsmStr> + : Instruction { let Namespace = "X86"; bits<8> Opcode = opcod; @@ -123,11 +124,14 @@ class DF { bits<4> Prefix = 10; } //===----------------------------------------------------------------------===// // Instruction templates... -class I<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, NoImm, ops, asm>; - -class Ii8 <bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm8 , ops, asm>; -class Ii16<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm16, ops, asm>; -class Ii32<bits<8> o, Format f, dag ops, string asm> : X86Inst<o, f, Imm32, ops, asm>; +class I<bits<8> o, Format f, dag ops, string asm> + : X86Inst<o, f, NoImm, ops, asm>; +class Ii8 <bits<8> o, Format f, dag ops, string asm> + : X86Inst<o, f, Imm8 , ops, asm>; +class Ii16<bits<8> o, Format f, dag ops, string asm> + : X86Inst<o, f, Imm16, ops, asm>; +class Ii32<bits<8> o, Format f, dag ops, string asm> + : X86Inst<o, f, Imm32, ops, asm>; //===----------------------------------------------------------------------===// // Instruction list... @@ -190,42 +194,61 @@ let isCall = 1 in def LEAVE : I<0xC9, RawFrm, (ops), "leave">, Imp<[EBP,ESP],[EBP,ESP]>; def POP32r : I<0x58, AddRegFrm, - (ops R32:$reg), "pop $reg">, Imp<[ESP],[ESP]>; + (ops R32:$reg), "pop{l} $reg">, Imp<[ESP],[ESP]>; -let isTwoAddress = 1 in // R32 = bswap R32 +let isTwoAddress = 1 in // R32 = bswap R32 def BSWAP32r : I<0xC8, AddRegFrm, - (ops R32:$dst, R32:$src), "bswap $dst">, TB; + (ops R32:$dst, R32:$src), "bswap{l} $dst">, TB; def XCHG8rr : I<0x86, MRMDestReg, // xchg R8, R8 - (ops R8:$src1, R8:$src2), "xchg $src1, $src2">; + (ops R8:$src1, R8:$src2), + "xchg{b} {$src2|$src1}, {$src1|$src2}">; def XCHG16rr : I<0x87, MRMDestReg, // xchg R16, R16 - (ops R16:$src1, R16:$src2), "xchg $src1, $src2">, OpSize; + (ops R16:$src1, R16:$src2), + "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; def XCHG32rr : I<0x87, MRMDestReg, // xchg R32, R32 - (ops R32:$src1, R32:$src2), "xchg $src1, $src2">; - -def XCHG8mr : I<0x86, MRMDestMem, (ops i8mem:$src1, R8:$src2), "xchg $src1, $src2">; -def XCHG16mr : I<0x87, MRMDestMem, (ops i16mem:$src1, R16:$src2), "xchg $src1, $src2">, OpSize; -def XCHG32mr : I<0x87, MRMDestMem, (ops i32mem:$src1, R32:$src2), "xchg $src1, $src2">; -def XCHG8rm : I<0x86, MRMSrcMem , (ops R8:$src1, i8mem:$src2), "xchg $src1, $src2">; -def XCHG16rm : I<0x87, MRMSrcMem , (ops R16:$src1, i16mem:$src2), "xchg $src1, $src2">, OpSize; -def XCHG32rm : I<0x87, MRMSrcMem , (ops R32:$src1, i32mem:$src2), "xchg $src1, $src2">; - -def LEA16r : I<0x8D, MRMSrcMem, (ops R16:$dst, i32mem:$src), "lea $dst, $src">, OpSize; -def LEA32r : I<0x8D, MRMSrcMem, (ops R32:$dst, i32mem:$src), "lea $dst, $src">; - - -def REP_MOVSB : I<0xA4, RawFrm, (ops), "rep movsb">, + (ops R32:$src1, R32:$src2), + "xchg{l} {$src2|$src1}, {$src1|$src2}">; + +def XCHG8mr : I<0x86, MRMDestMem, + (ops i8mem:$src1, R8:$src2), + "xchg{b} {$src2|$src1}, {$src1|$src2}">; +def XCHG16mr : I<0x87, MRMDestMem, + (ops i16mem:$src1, R16:$src2), + "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; +def XCHG32mr : I<0x87, MRMDestMem, + (ops i32mem:$src1, R32:$src2), + "xchg{l} {$src2|$src1}, {$src1|$src2}">; +def XCHG8rm : I<0x86, MRMSrcMem, + (ops R8:$src1, i8mem:$src2), + "xchg{b} {$src2|$src1}, {$src1|$src2}">; +def XCHG16rm : I<0x87, MRMSrcMem, + (ops R16:$src1, i16mem:$src2), + "xchg{w} {$src2|$src1}, {$src1|$src2}">, OpSize; +def XCHG32rm : I<0x87, MRMSrcMem, + (ops R32:$src1, i32mem:$src2), + "xchg{l} {$src2|$src1}, {$src1|$src2}">; + +def LEA16r : I<0x8D, MRMSrcMem, + (ops R16:$dst, i32mem:$src), + "lea{w} {$src|$dst}, {$dst|$src}">, OpSize; +def LEA32r : I<0x8D, MRMSrcMem, + (ops R32:$dst, i32mem:$src), + "lea{l} {$src|$dst}, {$dst|$src}">; + + +def REP_MOVSB : I<0xA4, RawFrm, (ops), "{rep;movsb|rep movsb}">, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; -def REP_MOVSW : I<0xA5, RawFrm, (ops), "rep movsw">, +def REP_MOVSW : I<0xA5, RawFrm, (ops), "{rep;movsw|rep movsw}">, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP, OpSize; -def REP_MOVSD : I<0xA5, RawFrm, (ops), "rep movsd">, +def REP_MOVSD : I<0xA5, RawFrm, (ops), "{rep;movsd|rep movsd}">, Imp<[ECX,EDI,ESI], [ECX,EDI,ESI]>, REP; -def REP_STOSB : I<0xAA, RawFrm, (ops), "rep stosb">, +def REP_STOSB : I<0xAA, RawFrm, (ops), "{rep;stosb|rep stosb}">, Imp<[AL,ECX,EDI], [ECX,EDI]>, REP; -def REP_STOSW : I<0xAB, RawFrm, (ops), "rep stosw">, +def REP_STOSW : I<0xAB, RawFrm, (ops), "{rep;stosw|rep stosw}">, Imp<[AX,ECX,EDI], [ECX,EDI]>, REP, OpSize; -def REP_STOSD : I<0xAB, RawFrm, (ops), "rep stosd">, +def REP_STOSD : I<0xAB, RawFrm, (ops), "{rep;stosd|rep stosd}">, Imp<[EAX,ECX,EDI], [ECX,EDI]>, REP; @@ -233,98 +256,122 @@ def REP_STOSD : I<0xAB, RawFrm, (ops), "rep stosd">, // Input/Output Instructions... // def IN8rr : I<0xEC, RawFrm, (ops), - "in %AL, %DX">, Imp<[DX], [AL]>; + "in{b} {%DX, %AL|AL, DX}">, Imp<[DX], [AL]>; def IN16rr : I<0xED, RawFrm, (ops), - "in %AX, %DX">, Imp<[DX], [AX]>, OpSize; + "in{w} {%DX, %AX|AX, DX}">, Imp<[DX], [AX]>, OpSize; def IN32rr : I<0xED, RawFrm, (ops), - "in %EAX, %DX">, Imp<[DX],[EAX]>; + "in{l} {%DX, %EAX|EAX, DX}">, Imp<[DX],[EAX]>; def IN8ri : Ii16<0xE4, RawFrm, (ops i16imm:$port), - "in %AL, $port">, Imp<[], [AL]>; + "in{b} {$port, %AL|AL, $port}">, Imp<[], [AL]>; def IN16ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), - "in %AX, $port">, Imp<[], [AX]>, OpSize; + "in{w} {$port, %AX|AX, $port}">, Imp<[], [AX]>, OpSize; def IN32ri : Ii16<0xE5, RawFrm, (ops i16imm:$port), - "in %EAX, $port">, Imp<[],[EAX]>; + "in{l} {$port, %EAX|EAX, $port}">, Imp<[],[EAX]>; def OUT8rr : I<0xEE, RawFrm, (ops), - "out %DX, %AL">, Imp<[DX, AL], []>; + "out{b} {%AL, %DX|DX, AL}">, Imp<[DX, AL], []>; def OUT16rr : I<0xEF, RawFrm, (ops), - "out %DX, %AX">, Imp<[DX, AX], []>, OpSize; + "out{w} {%AX, %DX|DX, AX}">, Imp<[DX, AX], []>, OpSize; def OUT32rr : I<0xEF, RawFrm, (ops), - "out %DX, %EAX">, Imp<[DX, EAX], []>; + "out{l} {%EAX, %DX|DX, EAX}">, Imp<[DX, EAX], []>; def OUT8ir : Ii16<0xE6, RawFrm, (ops i16imm:$port), - "out $port, %AL">, Imp<[AL], []>; + "out{b} {%AL, $port|$port, AL}">, Imp<[AL], []>; def OUT16ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), - "out $port, %AX">, Imp<[AX], []>, OpSize; + "out{w} {%AX, $port|$port, AX}">, Imp<[AX], []>, OpSize; def OUT32ir : Ii16<0xE7, RawFrm, (ops i16imm:$port), - "out $port, %EAX">, Imp<[EAX], []>; + "out{l} {%EAX, $port|$port, %EAX}">, Imp<[EAX], []>; //===----------------------------------------------------------------------===// // Move Instructions... // -def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), "mov $dst, $src">; -def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), "mov $dst, $src">, OpSize; -def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), "mov $dst, $src">; -def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), "mov $dst, $src">; -def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), "mov $dst, $src">, OpSize; -def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), "mov $dst, $src">; -def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), "mov $dst, $src">; -def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), "mov $dst, $src">, OpSize; -def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), "mov $dst, $src">; - -def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), "mov $dst, $src">; -def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), "mov $dst, $src">, OpSize; -def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), "mov $dst, $src">; - -def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), "mov $dst, $src">; -def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), "mov $dst, $src">, OpSize; -def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), "mov $dst, $src">; +def MOV8rr : I<0x88, MRMDestReg, (ops R8 :$dst, R8 :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16rr : I<0x89, MRMDestReg, (ops R16:$dst, R16:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32rr : I<0x89, MRMDestReg, (ops R32:$dst, R32:$src), + "mov{l} {$src, $dst|$dst, $src}">; +def MOV8ri : Ii8 <0xB0, AddRegFrm, (ops R8 :$dst, i8imm :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16ri : Ii16<0xB8, AddRegFrm, (ops R16:$dst, i16imm:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32ri : Ii32<0xB8, AddRegFrm, (ops R32:$dst, i32imm:$src), + "mov{l} {$src, $dst|$dst, $src}">; +def MOV8mi : Ii8 <0xC6, MRM0m, (ops i8mem :$dst, i8imm :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16mi : Ii16<0xC7, MRM0m, (ops i16mem:$dst, i16imm:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32mi : Ii32<0xC7, MRM0m, (ops i32mem:$dst, i32imm:$src), + "mov{l} {$src, $dst|$dst, $src}">; + +def MOV8rm : I<0x8A, MRMSrcMem, (ops R8 :$dst, i8mem :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16rm : I<0x8B, MRMSrcMem, (ops R16:$dst, i16mem:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32rm : I<0x8B, MRMSrcMem, (ops R32:$dst, i32mem:$src), + "mov{l} {$src, $dst|$dst, $src}">; + +def MOV8mr : I<0x88, MRMDestMem, (ops i8mem :$dst, R8 :$src), + "mov{b} {$src, $dst|$dst, $src}">; +def MOV16mr : I<0x89, MRMDestMem, (ops i16mem:$dst, R16:$src), + "mov{w} {$src, $dst|$dst, $src}">, OpSize; +def MOV32mr : I<0x89, MRMDestMem, (ops i32mem:$dst, R32:$src), + "mov{l} {$src, $dst|$dst, $src}">; //===----------------------------------------------------------------------===// // Fixed-Register Multiplication and Division Instructions... // // Extra precision multiplication -def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul $src">, +def MUL8r : I<0xF6, MRM4r, (ops R8:$src), "mul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*R8 -def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul $src">, +def MUL16r : I<0xF7, MRM4r, (ops R16:$src), "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*R16 -def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul $src">, +def MUL32r : I<0xF7, MRM4r, (ops R32:$src), "mul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*R32 def MUL8m : I<0xF6, MRM4m, (ops i8mem :$src), - "mul $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] + "mul{b} $src">, Imp<[AL],[AX]>; // AL,AH = AL*[mem8] def MUL16m : I<0xF7, MRM4m, (ops i16mem:$src), - "mul $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] + "mul{w} $src">, Imp<[AX],[AX,DX]>, OpSize; // AX,DX = AX*[mem16] def MUL32m : I<0xF7, MRM4m, (ops i32mem:$src), - "mul $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] + "mul{l} $src">, Imp<[EAX],[EAX,EDX]>; // EAX,EDX = EAX*[mem32] // unsigned division/remainder -def DIV8r : I<0xF6, MRM6r, (ops R8:$src), "div $src">, - Imp<[AX],[AX]>; // AX/r8 = AL,AH -def DIV16r : I<0xF7, MRM6r, (ops R16:$src), "div $src">, - Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX -def DIV32r : I<0xF7, MRM6r, (ops R32:$src), "div $src">, - Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX -def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), "div $src">, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH -def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), "div $src">, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX -def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), "div $src">, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX +def DIV8r : I<0xF6, MRM6r, (ops R8:$src), // AX/r8 = AL,AH + "div{b} $src">, Imp<[AX],[AX]>; +def DIV16r : I<0xF7, MRM6r, (ops R16:$src), // DX:AX/r16 = AX,DX + "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; +def DIV32r : I<0xF7, MRM6r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX + "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; +def DIV8m : I<0xF6, MRM6m, (ops i8mem:$src), // AX/[mem8] = AL,AH + "div{b} $src">, Imp<[AX],[AX]>; +def DIV16m : I<0xF7, MRM6m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX + "div{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; +def DIV32m : I<0xF7, MRM6m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX + "div{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; // Signed division/remainder. -def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), "idiv $src">, - Imp<[AX],[AX]>; // AX/r8 = AL,AH -def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), "idiv $src">, - Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/r16 = AX,DX -def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), "idiv $src">, - Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/r32 = EAX,EDX -def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), "idiv $src">, Imp<[AX],[AX]>; // AX/[mem8] = AL,AH -def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), "idiv $src">, Imp<[AX,DX],[AX,DX]>, OpSize; // DX:AX/[mem16] = AX,DX -def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), "idiv $src">, Imp<[EAX,EDX],[EAX,EDX]>; // EDX:EAX/[mem32] = EAX,EDX +def IDIV8r : I<0xF6, MRM7r, (ops R8:$src), // AX/r8 = AL,AH + "idiv{b} $src">, Imp<[AX],[AX]>; +def IDIV16r: I<0xF7, MRM7r, (ops R16:$src), // DX:AX/r16 = AX,DX + "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; +def IDIV32r: I<0xF7, MRM7r, (ops R32:$src), // EDX:EAX/r32 = EAX,EDX + "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; +def IDIV8m : I<0xF6, MRM7m, (ops i8mem:$src), // AX/[mem8] = AL,AH + "idiv{b} $src">, Imp<[AX],[AX]>; +def IDIV16m: I<0xF7, MRM7m, (ops i16mem:$src), // DX:AX/[mem16] = AX,DX + "idiv{w} $src">, Imp<[AX,DX],[AX,DX]>, OpSize; +def IDIV32m: I<0xF7, MRM7m, (ops i32mem:$src), // EDX:EAX/[mem32] = EAX,EDX + "idiv{l} $src">, Imp<[EAX,EDX],[EAX,EDX]>; // Sign-extenders for division. -def CBW : I<0x98, RawFrm, (ops), "cbw">, Imp<[AL],[AH]>; // AX = signext(AL) -def CWD : I<0x99, RawFrm, (ops), "cwd">, Imp<[AX],[DX]>; // DX:AX = signext(AX) -def CDQ : I<0x99, RawFrm, (ops), "cdq">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) +def CBW : I<0x98, RawFrm, (ops), + "{cbtw|cbw}">, Imp<[AL],[AH]>; // AX = signext(AL) +def CWD : I<0x99, RawFrm, (ops), + "{cwtl|cwd}">, Imp<[AX],[DX]>; // DX:AX = signext(AX) +def CDQ : I<0x99, RawFrm, (ops), + "{cltd|cdq}">, Imp<[EAX],[EDX]>; // EDX:EAX = signext(EAX) //===----------------------------------------------------------------------===// @@ -333,469 +380,681 @@ def CDQ : I<0x99, RawFrm, (ops), "cdq">, Imp<[EAX],[EDX]>; // EDX:EAX = signext( let isTwoAddress = 1 in { // Conditional moves -def CMOVB16rr : I<0x42, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovb $dst, $src2">, TB, OpSize; // if <u, R16 = R16 -def CMOVB16rm : I<0x42, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovb $dst, $src2">, TB, OpSize; // if <u, R16 = [mem16] -def CMOVB32rr : I<0x42, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovb $dst, $src2">, TB; // if <u, R32 = R32 -def CMOVB32rm : I<0x42, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovb $dst, $src2">, TB; // if <u, R32 = [mem32] - -def CMOVAE16rr: I<0x43, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovae $dst, $src2">, TB, OpSize; // if >=u, R16 = R16 -def CMOVAE16rm: I<0x43, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovae $dst, $src2">, TB, OpSize; // if >=u, R16 = [mem16] -def CMOVAE32rr: I<0x43, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovae $dst, $src2">, TB; // if >=u, R32 = R32 -def CMOVAE32rm: I<0x43, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovae $dst, $src2">, TB; // if >=u, R32 = [mem32] - -def CMOVE16rr : I<0x44, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmove $dst, $src2">, TB, OpSize; // if ==, R16 = R16 -def CMOVE16rm : I<0x44, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmove $dst, $src2">, TB, OpSize; // if ==, R16 = [mem16] -def CMOVE32rr : I<0x44, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmove $dst, $src2">, TB; // if ==, R32 = R32 -def CMOVE32rm : I<0x44, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmove $dst, $src2">, TB; // if ==, R32 = [mem32] - -def CMOVNE16rr: I<0x45, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovne $dst, $src2">, TB, OpSize; // if !=, R16 = R16 -def CMOVNE16rm: I<0x45, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovne $dst, $src2">, TB, OpSize; // if !=, R16 = [mem16] -def CMOVNE32rr: I<0x45, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovne $dst, $src2">, TB; // if !=, R32 = R32 -def CMOVNE32rm: I<0x45, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovne $dst, $src2">, TB; // if !=, R32 = [mem32] - -def CMOVBE16rr: I<0x46, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovbe $dst, $src2">, TB, OpSize; // if <=u, R16 = R16 -def CMOVBE16rm: I<0x46, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovbe $dst, $src2">, TB, OpSize; // if <=u, R16 = [mem16] -def CMOVBE32rr: I<0x46, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovbe $dst, $src2">, TB; // if <=u, R32 = R32 -def CMOVBE32rm: I<0x46, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovbe $dst, $src2">, TB; // if <=u, R32 = [mem32] - -def CMOVA16rr : I<0x47, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmova $dst, $src2">, TB, OpSize; // if >u, R16 = R16 -def CMOVA16rm : I<0x47, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmova $dst, $src2">, TB, OpSize; // if >u, R16 = [mem16] -def CMOVA32rr : I<0x47, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmova $dst, $src2">, TB; // if >u, R32 = R32 -def CMOVA32rm : I<0x47, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmova $dst, $src2">, TB; // if >u, R32 = [mem32] - -def CMOVS16rr : I<0x48, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovs $dst, $src2">, TB, OpSize; // if signed, R16 = R16 -def CMOVS16rm : I<0x48, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovs $dst, $src2">, TB, OpSize; // if signed, R16 = [mem16] -def CMOVS32rr : I<0x48, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovs $dst, $src2">, TB; // if signed, R32 = R32 -def CMOVS32rm : I<0x48, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovs $dst, $src2">, TB; // if signed, R32 = [mem32] - -def CMOVNS16rr: I<0x49, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovns $dst, $src2">, TB, OpSize; // if !signed, R16 = R16 -def CMOVNS16rm: I<0x49, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovns $dst, $src2">, TB, OpSize; // if !signed, R16 = [mem16] -def CMOVNS32rr: I<0x49, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovns $dst, $src2">, TB; // if !signed, R32 = R32 -def CMOVNS32rm: I<0x49, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovns $dst, $src2">, TB; // if !signed, R32 = [mem32] - -def CMOVL16rr : I<0x4C, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovl $dst, $src2">, TB, OpSize; // if <s, R16 = R16 -def CMOVL16rm : I<0x4C, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovl $dst, $src2">, TB, OpSize; // if <s, R16 = [mem16] -def CMOVL32rr : I<0x4C, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovl $dst, $src2">, TB; // if <s, R32 = R32 -def CMOVL32rm : I<0x4C, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovl $dst, $src2">, TB; // if <s, R32 = [mem32] - -def CMOVGE16rr: I<0x4D, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovge $dst, $src2">, TB, OpSize; // if >=s, R16 = R16 -def CMOVGE16rm: I<0x4D, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovge $dst, $src2">, TB, OpSize; // if >=s, R16 = [mem16] -def CMOVGE32rr: I<0x4D, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovge $dst, $src2">, TB; // if >=s, R32 = R32 -def CMOVGE32rm: I<0x4D, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovge $dst, $src2">, TB; // if >=s, R32 = [mem32] - -def CMOVLE16rr: I<0x4E, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovle $dst, $src2">, TB, OpSize; // if <=s, R16 = R16 -def CMOVLE16rm: I<0x4E, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovle $dst, $src2">, TB, OpSize; // if <=s, R16 = [mem16] -def CMOVLE32rr: I<0x4E, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovle $dst, $src2">, TB; // if <=s, R32 = R32 -def CMOVLE32rm: I<0x4E, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovle $dst, $src2">, TB; // if <=s, R32 = [mem32] - -def CMOVG16rr : I<0x4F, MRMSrcReg, (ops R16:$dst, R16:$src1, R16:$src2), - "cmovg $dst, $src2">, TB, OpSize; // if >s, R16 = R16 -def CMOVG16rm : I<0x4F, MRMSrcMem, (ops R16:$dst, R16:$src1, i16mem:$src2), - "cmovg $dst, $src2">, TB, OpSize; // if >s, R16 = [mem16] -def CMOVG32rr : I<0x4F, MRMSrcReg, (ops R32:$dst, R32:$src1, R32:$src2), - "cmovg $dst, $src2">, TB; // if >s, R32 = R32 -def CMOVG32rm : I<0x4F, MRMSrcMem, (ops R32:$dst, R32:$src1, i32mem:$src2), - "cmovg $dst, $src2">, TB; // if >s, R32 = [mem32] +def CMOVB16rr : I<0x42, MRMSrcReg, // if <u, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVB16rm : I<0x42, MRMSrcMem, // if <u, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovb {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVB32rr : I<0x42, MRMSrcReg, // if <u, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovb {$src2, $dst|$dst, $src2}">, TB; +def CMOVB32rm : I<0x42, MRMSrcMem, // if <u, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovb {$src2, $dst|$dst, $src2}">, TB; + +def CMOVAE16rr: I<0x43, MRMSrcReg, // if >=u, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVAE16rm: I<0x43, MRMSrcMem, // if >=u, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovae {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVAE32rr: I<0x43, MRMSrcReg, // if >=u, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovae {$src2, $dst|$dst, $src2}">, TB; +def CMOVAE32rm: I<0x43, MRMSrcMem, // if >=u, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovae {$src2, $dst|$dst, $src2}">, TB; + +def CMOVE16rr : I<0x44, MRMSrcReg, // if ==, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVE16rm : I<0x44, MRMSrcMem, // if ==, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmove {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVE32rr : I<0x44, MRMSrcReg, // if ==, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmove {$src2, $dst|$dst, $src2}">, TB; +def CMOVE32rm : I<0x44, MRMSrcMem, // if ==, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmove {$src2, $dst|$dst, $src2}">, TB; + +def CMOVNE16rr: I<0x45, MRMSrcReg, // if !=, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNE16rm: I<0x45, MRMSrcMem, // if !=, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovne {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNE32rr: I<0x45, MRMSrcReg, // if !=, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovne {$src2, $dst|$dst, $src2}">, TB; +def CMOVNE32rm: I<0x45, MRMSrcMem, // if !=, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovne {$src2, $dst|$dst, $src2}">, TB; + +def CMOVBE16rr: I<0x46, MRMSrcReg, // if <=u, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVBE16rm: I<0x46, MRMSrcMem, // if <=u, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovbe {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVBE32rr: I<0x46, MRMSrcReg, // if <=u, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovbe {$src2, $dst|$dst, $src2}">, TB; +def CMOVBE32rm: I<0x46, MRMSrcMem, // if <=u, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovbe {$src2, $dst|$dst, $src2}">, TB; + +def CMOVA16rr : I<0x47, MRMSrcReg, // if >u, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVA16rm : I<0x47, MRMSrcMem, // if >u, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmova {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVA32rr : I<0x47, MRMSrcReg, // if >u, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmova {$src2, $dst|$dst, $src2}">, TB; +def CMOVA32rm : I<0x47, MRMSrcMem, // if >u, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmova {$src2, $dst|$dst, $src2}">, TB; + +def CMOVS16rr : I<0x48, MRMSrcReg, // if signed, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVS16rm : I<0x48, MRMSrcMem, // if signed, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovs {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVS32rr : I<0x48, MRMSrcReg, // if signed, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovs {$src2, $dst|$dst, $src2}">, TB; +def CMOVS32rm : I<0x48, MRMSrcMem, // if signed, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovs {$src2, $dst|$dst, $src2}">, TB; + +def CMOVNS16rr: I<0x49, MRMSrcReg, // if !signed, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNS16rm: I<0x49, MRMSrcMem, // if !signed, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovns {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVNS32rr: I<0x49, MRMSrcReg, // if !signed, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovns {$src2, $dst|$dst, $src2}">, TB; +def CMOVNS32rm: I<0x49, MRMSrcMem, // if !signed, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovns {$src2, $dst|$dst, $src2}">, TB; + +def CMOVL16rr : I<0x4C, MRMSrcReg, // if <s, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVL16rm : I<0x4C, MRMSrcMem, // if <s, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovl {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVL32rr : I<0x4C, MRMSrcReg, // if <s, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovl {$src2, $dst|$dst, $src2}">, TB; +def CMOVL32rm : I<0x4C, MRMSrcMem, // if <s, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovl {$src2, $dst|$dst, $src2}">, TB; + +def CMOVGE16rr: I<0x4D, MRMSrcReg, // if >=s, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVGE16rm: I<0x4D, MRMSrcMem, // if >=s, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovge {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVGE32rr: I<0x4D, MRMSrcReg, // if >=s, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovge {$src2, $dst|$dst, $src2}">, TB; +def CMOVGE32rm: I<0x4D, MRMSrcMem, // if >=s, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovge {$src2, $dst|$dst, $src2}">, TB; + +def CMOVLE16rr: I<0x4E, MRMSrcReg, // if <=s, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVLE16rm: I<0x4E, MRMSrcMem, // if <=s, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovle {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVLE32rr: I<0x4E, MRMSrcReg, // if <=s, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovle {$src2, $dst|$dst, $src2}">, TB; +def CMOVLE32rm: I<0x4E, MRMSrcMem, // if <=s, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovle {$src2, $dst|$dst, $src2}">, TB; + +def CMOVG16rr : I<0x4F, MRMSrcReg, // if >s, R16 = R16 + (ops R16:$dst, R16:$src1, R16:$src2), + "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVG16rm : I<0x4F, MRMSrcMem, // if >s, R16 = [mem16] + (ops R16:$dst, R16:$src1, i16mem:$src2), + "cmovg {$src2, $dst|$dst, $src2}">, TB, OpSize; +def CMOVG32rr : I<0x4F, MRMSrcReg, // if >s, R32 = R32 + (ops R32:$dst, R32:$src1, R32:$src2), + "cmovg {$src2, $dst|$dst, $src2}">, TB; +def CMOVG32rm : I<0x4F, MRMSrcMem, // if >s, R32 = [mem32] + (ops R32:$dst, R32:$src1, i32mem:$src2), + "cmovg {$src2, $dst|$dst, $src2}">, TB; // unary instructions -def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg $dst">; -def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg $dst">, OpSize; -def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg $dst">; +def NEG8r : I<0xF6, MRM3r, (ops R8 :$dst, R8 :$src), "neg{b} $dst">; +def NEG16r : I<0xF7, MRM3r, (ops R16:$dst, R16:$src), "neg{w} $dst">, OpSize; +def NEG32r : I<0xF7, MRM3r, (ops R32:$dst, R32:$src), "neg{l} $dst">; let isTwoAddress = 0 in { - def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg $dst">; - def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg $dst">, OpSize; - def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg $dst">; + def NEG8m : I<0xF6, MRM3m, (ops i8mem :$dst), "neg{b} $dst">; + def NEG16m : I<0xF7, MRM3m, (ops i16mem:$dst), "neg{w} $dst">, OpSize; + def NEG32m : I<0xF7, MRM3m, (ops i32mem:$dst), "neg{l} $dst">; } -def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not $dst">; -def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not $dst">, OpSize; -def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not $dst">; +def NOT8r : I<0xF6, MRM2r, (ops R8 :$dst, R8 :$src), "not{b} $dst">; +def NOT16r : I<0xF7, MRM2r, (ops R16:$dst, R16:$src), "not{w} $dst">, OpSize; +def NOT32r : I<0xF7, MRM2r, (ops R32:$dst, R32:$src), "not{l} $dst">; let isTwoAddress = 0 in { - def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not $dst">; - def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not $dst">, OpSize; - def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not $dst">; + def NOT8m : I<0xF6, MRM2m, (ops i8mem :$dst), "not{b} $dst">; + def NOT16m : I<0xF7, MRM2m, (ops i16mem:$dst), "not{w} $dst">, OpSize; + def NOT32m : I<0xF7, MRM2m, (ops i32mem:$dst), "not{l} $dst">; } -def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc $dst">; -def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc $dst">, OpSize; -def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc $dst">; +def INC8r : I<0xFE, MRM0r, (ops R8 :$dst, R8 :$src), "inc{b} $dst">; +def INC16r : I<0xFF, MRM0r, (ops R16:$dst, R16:$src), "inc{w} $dst">, OpSize; +def INC32r : I<0xFF, MRM0r, (ops R32:$dst, R32:$src), "inc{l} $dst">; let isTwoAddress = 0 in { - def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc $dst">; - def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc $dst">, OpSize; - def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc $dst">; + def INC8m : I<0xFE, MRM0m, (ops i8mem :$dst), "inc{b} $dst">; + def INC16m : I<0xFF, MRM0m, (ops i16mem:$dst), "inc{w} $dst">, OpSize; + def INC32m : I<0xFF, MRM0m, (ops i32mem:$dst), "inc{l} $dst">; } -def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec $dst">; -def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec $dst">, OpSize; -def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec $dst">; +def DEC8r : I<0xFE, MRM1r, (ops R8 :$dst, R8 :$src), "dec{b} $dst">; +def DEC16r : I<0xFF, MRM1r, (ops R16:$dst, R16:$src), "dec{w} $dst">, OpSize; +def DEC32r : I<0xFF, MRM1r, (ops R32:$dst, R32:$src), "dec{l} $dst">; let isTwoAddress = 0 in { - def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec $dst">; - def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec $dst">, OpSize; - def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec $dst">; + def DEC8m : I<0xFE, MRM1m, (ops i8mem :$dst), "dec{b} $dst">; + def DEC16m : I<0xFF, MRM1m, (ops i16mem:$dst), "dec{w} $dst">, OpSize; + def DEC32m : I<0xFF, MRM1m, (ops i32mem:$dst), "dec{l} $dst">; } // Logical operators... -def AND8rr : I<0x20, MRMDestReg, (ops R8 :$dst, R8 :$src1, R8 :$src2), "and $dst, $src2">; -def AND16rr : I<0x21, MRMDestReg, (ops R16:$dst, R16:$src1, R16:$src2), "and $dst, $src2">, OpSize; -def AND32rr : I<0x21, MRMDestReg, (ops R32:$dst, R32:$src1, R32:$src2), "and $dst, $src2">; - -def AND8rm : I<0x22, MRMSrcMem , (ops R8 :$dst, R8 :$src1, i8mem :$src2), "and $dst, $src2">; -def AND16rm : I<0x23, MRMSrcMem , (ops R16:$dst, R16:$src1, i16mem:$src2), "and $dst, $src2">, OpSize; -def AND32rm : I<0x23, MRMSrcMem , (ops R32:$dst, R32:$src1, i32mem:$src2), "and $dst, $src2">; - -def AND8ri : Ii8 <0x80, MRM4r, (ops R8 :$dst, R8 :$src1, i8imm :$src2), - "and $dst, $src2">; -def AND16ri : Ii16<0x81, MRM4r, (ops R16:$dst, R16:$src1, i16imm:$src2), - "and $dst, $src2">, OpSize; -def AND32ri : Ii32<0x81, MRM4r, (ops R32:$dst, R32:$src1, i32imm:$src2), - "and $dst, $src2">; -def AND16ri8 : Ii8<0x83, MRM4r, (ops R16:$dst, R16:$src1, i8imm:$src2), - "and $dst, $src2" >, OpSize; -def AND32ri8 : Ii8<0x83, MRM4r, (ops R32:$dst, R32:$src1, i8imm:$src2), - "and $dst, $src2">; +def AND8rr : I<0x20, MRMDestReg, + (ops R8 :$dst, R8 :$src1, R8 :$src2), + "and{b} {$src2, $dst|$dst, $src2}">; +def AND16rr : I<0x21, MRMDestReg, + (ops R16:$dst, R16:$src1, R16:$src2), + "and{w} {$src2, $dst|$dst, $src2}">, OpSize; +def AND32rr : I<0x21, MRMDestReg, + (ops R32:$dst, R32:$src1, R32:$src2), + "and{l} {$src2, $dst|$dst, $src2}">; + +def AND8rm : I<0x22, MRMSrcMem, + (ops R8 :$dst, R8 :$src1, i8mem :$src2), + "and{b} {$src2, $dst|$dst, $src2}">; +def AND16rm : I<0x23, MRMSrcMem, + (ops R16:$dst, R16:$src1, i16mem:$src2), + "and{w} {$src2, $dst|$dst, $src2}">, OpSize; +def AND32rm : I<0x23, MRMSrcMem, + (ops R32:$dst, R32:$src1, i32mem:$src2), + "and{l} {$src2, $dst|$dst, $src2}">; + +def AND8ri : Ii8<0x80, MRM4r, + (ops R8 :$dst, R8 :$src1, i8imm :$src2), + "and{b} {$src2, $dst|$dst, $src2}">; +def AND16ri : Ii16<0x81, MRM4r, + (ops R16:$dst, R16:$src1, i16imm:$src2), + "and{w} {$src2, $dst|$dst, $src2}">, OpSize; +def AND32ri : Ii32<0x81, MRM4r, + (ops R32:$dst, R32:$src1, i32imm:$src2), + "and{l} {$src2, $dst|$dst, $src2}">; +def AND16ri8 : Ii8<0x83, MRM4r, + (ops R16:$dst, R16:$src1, i8imm:$src2), + "and{w} {$src2, $dst|$dst, $src2}" >, OpSize; +def AND32ri8 : Ii8<0x83, MRM4r, + (ops R32:$dst, R32:$src1, i8imm:$src2), + "and{l} {$src2, $dst|$dst, $src2}">; let isTwoAddress = 0 in { - def AND8mr : I<0x20, MRMDestMem, (ops i8mem :$dst, R8 :$src), "and $dst, $src">; - def AND16mr : I<0x21, MRMDestMem, (ops i16mem:$dst, R16:$src), "and $dst, $src">, OpSize; - def AND32mr : I<0x21, MRMDestMem, (ops i32mem:$dst, R32:$src), "and $dst, $src">; - def AND8mi : Ii8 <0x80, MRM4m, (ops i8mem :$dst, i8imm :$src), "and $dst, $src">; - def AND16mi : Ii16<0x81, MRM4m, (ops i16mem:$dst, i16imm:$src), "and $dst, $src">, OpSize; - def AND32mi : Ii32<0x81, MRM4m, (ops i32mem:$dst, i32imm:$src), "and $dst, $src">; - def AND16mi8 : Ii8 <0x83, MRM4m, (ops i16mem:$dst, i8imm :$src), "and $dst, $src">, OpSize; - def AND32mi8 : Ii8 <0x83, MRM4m, (ops i32mem:$dst, i8imm :$src), "and $dst, $src">; + def AND8mr : I<0x20, MRMDestMem, + (ops i8mem :$dst, R8 :$src), + "and{b} {$src, $dst|$dst, $src}">; + def AND16mr : I<0x21, MRMDestMem, + (ops i16mem:$dst, R16:$src), + "and{w} {$src, $dst|$dst, $src}">, OpSize; + def AND32mr : I<0x21, MRMDestMem, + (ops i32mem:$dst, R32:$src), + "and{l} {$src, $dst|$dst, $src}">; + def AND8mi : Ii8<0x80, MRM4m, + (ops i8mem :$dst, i8imm :$src), + "and{b} {$src, $dst|$dst, $src}">; |