diff options
| -rw-r--r-- | lib/Target/MSP430/MSP430ISelLowering.cpp | 1 | ||||
| -rw-r--r-- | test/CodeGen/MSP430/Inst16mm.ll | 2 | ||||
| -rw-r--r-- | test/CodeGen/MSP430/indirectbr2.ll | 2 |
3 files changed, 2 insertions, 3 deletions
diff --git a/lib/Target/MSP430/MSP430ISelLowering.cpp b/lib/Target/MSP430/MSP430ISelLowering.cpp index dc37431517..e837ef8897 100644 --- a/lib/Target/MSP430/MSP430ISelLowering.cpp +++ b/lib/Target/MSP430/MSP430ISelLowering.cpp @@ -80,7 +80,6 @@ MSP430TargetLowering::MSP430TargetLowering(MSP430TargetMachine &tm) : setStackPointerRegisterToSaveRestore(MSP430::SPW); setBooleanContents(ZeroOrOneBooleanContent); setBooleanVectorContents(ZeroOrOneBooleanContent); // FIXME: Is this correct? - setSchedulingPreference(Sched::Latency); // We have post-incremented loads / stores. setIndexedLoadAction(ISD::POST_INC, MVT::i8, Legal); diff --git a/test/CodeGen/MSP430/Inst16mm.ll b/test/CodeGen/MSP430/Inst16mm.ll index 2337c2c0f2..d4ae811ac8 100644 --- a/test/CodeGen/MSP430/Inst16mm.ll +++ b/test/CodeGen/MSP430/Inst16mm.ll @@ -64,6 +64,6 @@ entry: %0 = load i16* %retval ; <i16> [#uses=1] ret i16 %0 ; CHECK: mov2: -; CHECK: mov.w 0(r1), 4(r1) ; CHECK: mov.w 2(r1), 6(r1) +; CHECK: mov.w 0(r1), 4(r1) } diff --git a/test/CodeGen/MSP430/indirectbr2.ll b/test/CodeGen/MSP430/indirectbr2.ll index 93cfb2506b..dc2abf5cd0 100644 --- a/test/CodeGen/MSP430/indirectbr2.ll +++ b/test/CodeGen/MSP430/indirectbr2.ll @@ -5,7 +5,7 @@ define internal i16 @foo(i16 %i) nounwind { entry: %tmp1 = getelementptr inbounds [5 x i8*]* @C.0.2070, i16 0, i16 %i ; <i8**> [#uses=1] %gotovar.4.0 = load i8** %tmp1, align 4 ; <i8*> [#uses=1] -; CHECK: mov.w .LC.0.2070(r15), pc +; CHECK: mov.w .LC.0.2070(r12), pc indirectbr i8* %gotovar.4.0, [label %L5, label %L4, label %L3, label %L2, label %L1] L5: ; preds = %bb2 |