4 files changed, 55 insertions, 31 deletions
diff --git a/include/llvm/CodeGen/RegisterAllocation.h b/include/llvm/CodeGen/RegisterAllocation.h
index 161be18498..e552fbe887 100644
--- a/include/llvm/CodeGen/RegisterAllocation.h
+++ b/include/llvm/CodeGen/RegisterAllocation.h
@@ -9,16 +9,12 @@
 
 #include "llvm/Pass.h"
 class TargetMachine;
+class MethodPass;
 
 //----------------------------------------------------------------------------
 // Entry point for register allocation for a module
 //----------------------------------------------------------------------------
 
-class RegisterAllocation : public MethodPass {
-  TargetMachine &Target;
-public:
-  inline RegisterAllocation(TargetMachine &T) : Target(T) {}
-  bool runOnMethod(Method *M);
-};
+MethodPass *getRegisterAllocator(TargetMachine &T);
 
 #endif
diff --git a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
index 7efb469b45..46f045c5e2 100644
--- a/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/CodeGen/RegAlloc/PhyRegAlloc.cpp
@@ -32,21 +32,35 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
   clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
 
 
-bool RegisterAllocation::runOnMethod(Method *M) {
-  if (DEBUG_RA)
-    cerr << "\n******************** Method "<< M->getName()
-         << " ********************\n";
-    
-  MethodLiveVarInfo LVI(M);   // Analyze live varaibles
-  LVI.analyze();
+//----------------------------------------------------------------------------
+// RegisterAllocation pass front end...
+//----------------------------------------------------------------------------
+namespace {
+  class RegisterAllocator : public MethodPass {
+    TargetMachine &Target;
+  public:
+    inline RegisterAllocator(TargetMachine &T) : Target(T) {}
     
-  PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
-  PRA.allocateRegisters();
-
-  if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
-  return false;
+    bool runOnMethod(Method *M) {
+      if (DEBUG_RA)
+        cerr << "\n******************** Method "<< M->getName()
+             << " ********************\n";
+      
+      MethodLiveVarInfo LVI(M);   // Analyze live varaibles
+      LVI.analyze();
+      
+      PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
+      PRA.allocateRegisters();
+      
+      if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
+      return false;
+    }
+  };
 }
 
+MethodPass *getRegisterAllocator(TargetMachine &T) {
+  return new RegisterAllocator(T);
+}
 
 //----------------------------------------------------------------------------
 // Constructor: Init local composite objects and create register classes.
diff --git a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
index 7efb469b45..46f045c5e2 100644
--- a/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
+++ b/lib/Target/SparcV9/RegAlloc/PhyRegAlloc.cpp
@@ -32,21 +32,35 @@ cl::Enum<RegAllocDebugLevel_t> DEBUG_RA("dregalloc", cl::NoFlags,
   clEnumValN(RA_DEBUG_Verbose, "v", "enable extra debug output"), 0);
 
 
-bool RegisterAllocation::runOnMethod(Method *M) {
-  if (DEBUG_RA)
-    cerr << "\n******************** Method "<< M->getName()
-         << " ********************\n";
-    
-  MethodLiveVarInfo LVI(M);   // Analyze live varaibles
-  LVI.analyze();
+//----------------------------------------------------------------------------
+// RegisterAllocation pass front end...
+//----------------------------------------------------------------------------
+namespace {
+  class RegisterAllocator : public MethodPass {
+    TargetMachine &Target;
+  public:
+    inline RegisterAllocator(TargetMachine &T) : Target(T) {}
     
-  PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
-  PRA.allocateRegisters();
-
-  if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
-  return false;
+    bool runOnMethod(Method *M) {
+      if (DEBUG_RA)
+        cerr << "\n******************** Method "<< M->getName()
+             << " ********************\n";
+      
+      MethodLiveVarInfo LVI(M);   // Analyze live varaibles
+      LVI.analyze();
+      
+      PhyRegAlloc PRA(M, Target, &LVI); // allocate registers
+      PRA.allocateRegisters();
+      
+      if (DEBUG_RA) cerr << "\nRegister allocation complete!\n";
+      return false;
+    }
+  };
 }
 
+MethodPass *getRegisterAllocator(TargetMachine &T) {
+  return new RegisterAllocator(T);
+}
 
 //----------------------------------------------------------------------------
 // Constructor: Init local composite objects and create register classes.
diff --git a/lib/Target/SparcV9/SparcV9TargetMachine.cpp b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
index b4e069453c..91e51d88d2 100644
--- a/lib/Target/SparcV9/SparcV9TargetMachine.cpp
+++ b/lib/Target/SparcV9/SparcV9TargetMachine.cpp
@@ -260,7 +260,7 @@ void UltraSparc::addPassesToEmitAssembly(PassManager &PM, std::ostream &Out) {
 
   //PM.add(new InstructionScheduling(*this));
 
-  PM.add(new RegisterAllocation(*this));
+  PM.add(getRegisterAllocator(*this));
   
   //PM.add(new OptimizeLeafProcedures());
   //PM.add(new DeleteFallThroughBranches());